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bcwc_pcie: Add DDR40 VTT stuff

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Signed-off-by: Patrik Jakobsson <patrik.r.jakobsson@gmail.com>
This commit is contained in:
Patrik Jakobsson
2014-07-01 01:39:11 +02:00
parent 943942124d
commit 78bb2704ca
2 changed files with 65 additions and 0 deletions
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50
bcwc_hw.c
View File

@@ -256,6 +256,7 @@ static int bcwc_hw_s2_init_ddr_controller_soc(struct bcwc_private *dev_priv)
u32 val;
u32 reg;
u32 step_size, vdl_fine, vdl_coarse;
u32 vtt_cons, vtt_ovr;
int ret, i;
/* Set DDR speed (450 MHz for now) */
@@ -464,6 +465,7 @@ static int bcwc_hw_s2_init_ddr_controller_soc(struct bcwc_private *dev_priv)
dev_info(&dev_priv->pdev->dev, "DDR40 PLL is locked after %d us\n", i);
/* Configure DDR40 VDL */
BCWC_S2_REG_WRITE(0, S2_DDR40_PHY_VDL_CTL);
bcwc_hw_pci_post(dev_priv);
@@ -561,6 +563,54 @@ static int bcwc_hw_s2_init_ddr_controller_soc(struct bcwc_private *dev_priv)
vdl_coarse, vdl_fine);
}
/* Configure Virtual VTT connections and override */
vtt_cons = 0x1cf7fff;
BCWC_S2_REG_WRITE(vtt_cons, S2_DDR40_PHY_VTT_CONNECTIONS);
bcwc_hw_pci_post(dev_priv);
vtt_ovr = 0x77fff;
BCWC_S2_REG_WRITE(vtt_ovr, S2_DDR40_PHY_VTT_OVERRIDE);
bcwc_hw_pci_post(dev_priv);
BCWC_S2_REG_WRITE(0x4, S2_DDR40_PHY_VTT_CTL);
bcwc_hw_pci_post(dev_priv);
dev_info(&dev_priv->pdev->dev, "Virtual VTT enabled");
/* Process, Voltage and Temperature compensation */
BCWC_S2_REG_WRITE(0xc0fff, S2_DDR40_PHY_ZQ_PVT_COMP_CTL);
bcwc_hw_pci_post(dev_priv);
BCWC_S2_REG_WRITE(0x2, S2_DDR40_PHY_DRV_PAD_CTL);
bcwc_hw_pci_post(dev_priv);
BCWC_S2_REG_WRITE(0x2, S2_2BA4);
bcwc_hw_pci_post(dev_priv);
val = 1000000 / dev_priv->ddr_speed;
reg = 4;
if (val >= 400) {
if (val > 900)
reg |= 0xff;
reg += 5;
}
BCWC_S2_REG_WRITE(reg, S2_2B60);
bcwc_hw_pci_post(dev_priv);
BCWC_S2_REG_WRITE(0x2, S2_2B64);
bcwc_hw_pci_post(dev_priv);
BCWC_S2_REG_WRITE(0x3, S2_2BAC);
bcwc_hw_pci_post(dev_priv);
BCWC_S2_REG_WRITE(0xff0fffff, S2_2BA0);
bcwc_hw_pci_post(dev_priv);
udelay(500);
/* FIXME: Unfinished */
return 0;

15
bcwc_reg.h
View File

@@ -74,17 +74,32 @@
#define S2_DDR40_PHY_PLL_CFG 0x2814
#define S2_DDR40_PHY_PLL_DIV 0x281c
#define S2_DDR40_AUX_CTL 0x2820
#define S2_DDR40_PHY_VDL_OVR_COARSE 0x2830
#define S2_DDR40_PHY_VDL_OVR_FINE 0x2834
#define S2_DDR40_PHY_ZQ_PVT_COMP_CTL 0x283c
#define S2_DDR40_PHY_DRV_PAD_CTL 0x2840
#define S2_DDR40_PHY_VDL_CTL 0x2848
#define S2_DDR40_PHY_VDL_STATUS 0x284c
#define S2_DDR40_PHY_VDL_CHAN_STATUS 0x2854
#define S2_DDR40_PHY_VTT_CTL 0x285c
#define S2_DDR40_PHY_VTT_STATUS 0x2860
#define S2_DDR40_PHY_VTT_CONNECTIONS 0x2864
#define S2_DDR40_PHY_VTT_OVERRIDE 0x2868
#define S2_DDR40_STRAP_CTL 0x28b0
#define S2_DDR40_STRAP_CTL_2 0x28b4
#define S2_DDR40_STRAP_STATUS 0x28b8
#define S2_2B60 0x2b60
#define S2_2B64 0x2b64
#define S2_2BA4 0x2ba4
#define S2_2BA8 0x2ba8
#define S2_2BA0 0x2ba0
#define S2_2BAC 0x2bac
/* On iomem with pointer at 0x0ff0 (Bar 4: 1MB) */
#define IRQ_IPC_NUM_CHAN 0xc3000