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	T1024RDB is a Freescale Reference Design Board that hosts the T1024 SoC. T1024RDB board Overview ----------------------- - T1024 SoC integrating two 64-bit e5500 cores up to 1.4GHz - CoreNet fabric supporting coherent and noncoherent transactions with prioritization and bandwidth allocation - 32-/64-bit DDR3L SDRAM memory controller with ECC and interleaving support - Accelerator: DPAA components consist of FMan, BMan, QMan, DCE and SEC - Ethernet interfaces: - Two 10M/100M/1G RGMII ports on-board - one 10Gbps XFI interface - PCIe: Three PCIe controllers: one PCIe Slot and two Mini-PCIe connectors. - SerDes: 4 lanes up to 10.3125GHz - IFC: 128MB NOR Flash, 512MB NAND Flash and CPLD - eSPI: 64MB N25Q512 SPI flash. - Deep Sleep power implementaion (wakeup from GPIO/Timer/Ethernet/USB) - USB: Two Type-A USB2.0 ports with internal PHY - eSDHC: Support SD, SDHC, SDXC and MMC/eMMC - I2C: Four I2C controllers - UART: Two UART serial ports Signed-off-by: Shengzhou Liu <Shengzhou.Liu@freescale.com> [York Sun: Fix ft_board_setup() type, fix MAINTAINERS for SECURE_BOOT Fix Kconfig by adding SUPPORT_SPL] Reviewed-by: York Sun <yorksun@freescale.com>
		
			
				
	
	
		
			33 lines
		
	
	
		
			883 B
		
	
	
	
		
			C
		
	
	
	
	
	
			
		
		
	
	
			33 lines
		
	
	
		
			883 B
		
	
	
	
		
			C
		
	
	
	
	
	
| /*
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|  * Copyright 2014 Freescale Semiconductor, Inc.
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|  *
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|  * SPDX-License-Identifier:	GPL-2.0+
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|  */
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| 
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| #include <common.h>
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| #include <asm/fsl_law.h>
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| #include <asm/mmu.h>
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| 
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| struct law_entry law_table[] = {
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| #ifndef CONFIG_SYS_NO_FLASH
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| 	SET_LAW(CONFIG_SYS_FLASH_BASE_PHYS, LAW_SIZE_256M, LAW_TRGT_IF_IFC),
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| #endif
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| #ifdef CONFIG_SYS_BMAN_MEM_PHYS
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| 	SET_LAW(CONFIG_SYS_BMAN_MEM_PHYS, LAW_SIZE_32M, LAW_TRGT_IF_BMAN),
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| #endif
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| #ifdef CONFIG_SYS_QMAN_MEM_PHYS
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| 	SET_LAW(CONFIG_SYS_QMAN_MEM_PHYS, LAW_SIZE_32M, LAW_TRGT_IF_QMAN),
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| #endif
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| #ifdef CONFIG_SYS_CPLD_BASE_PHYS
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| 	SET_LAW(CONFIG_SYS_CPLD_BASE_PHYS, LAW_SIZE_4K, LAW_TRGT_IF_IFC),
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| #endif
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| #ifdef CONFIG_SYS_DCSRBAR_PHYS
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| 	SET_LAW(CONFIG_SYS_DCSRBAR_PHYS, LAW_SIZE_4M, LAW_TRGT_IF_DCSR),
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| #endif
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| #ifdef CONFIG_SYS_NAND_BASE_PHYS
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| 	SET_LAW(CONFIG_SYS_NAND_BASE_PHYS, LAW_SIZE_64K, LAW_TRGT_IF_IFC),
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| #endif
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| };
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| 
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| int num_law_entries = ARRAY_SIZE(law_table);
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