Aneesh Bansal 467a40dfe3 powerpc/mpc85xx: SECURE BOOT- NAND secure boot target for P3041 ...

Secure Boot Target is added for NAND for P3041.
For mpc85xx SoCs, the core begins execution from address 0xFFFFFFFC.
In case of secure boot, this default address maps to Boot ROM.
The Boot ROM code requires that the bootloader(U-boot) must lie
in 0 to 3.5G address space i.e. 0x0 - 0xDFFFFFFF.

In case of NAND Secure Boot, CONFIG_SYS_RAMBOOT is enabled and CPC is
configured as SRAM. U-Boot binary will be located on SRAM configured
at address 0xBFF00000.
In the U-Boot code, TLB entries are created to map the virtual address
0xFFF00000 to physical address 0xBFF00000 of CPC configured as SRAM.

Signed-off-by: Saksham Jain <saksham@freescale.com>
Signed-off-by: Ruchika Gupta <ruchika.gupta@freescale.com>
Signed-off-by: Aneesh Bansal <aneesh.bansal@freescale.com>
Reviewed-by: York Sun <yorksun@freescale.com>

2015-07-31 08:50:18 -07:00

..

law.c

Add GPL-2.0+ SPDX-License-Identifier to source files

2013-07-24 09:44:38 -04:00

Makefile

Makefile: delete unnecessary CPPFLAGS settings

2013-12-13 09:18:45 -05:00

pci.c

Add GPL-2.0+ SPDX-License-Identifier to source files

2013-07-24 09:44:38 -04:00

tlb.c

powerpc/mpc85xx: SECURE BOOT- NAND secure boot target for P3041

2015-07-31 08:50:18 -07:00