mirror of
https://xff.cz/git/u-boot/
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83d290c56f
When U-Boot started using SPDX tags we were among the early adopters and there weren't a lot of other examples to borrow from. So we picked the area of the file that usually had a full license text and replaced it with an appropriate SPDX-License-Identifier: entry. Since then, the Linux Kernel has adopted SPDX tags and they place it as the very first line in a file (except where shebangs are used, then it's second line) and with slightly different comment styles than us. In part due to community overlap, in part due to better tag visibility and in part for other minor reasons, switch over to that style. This commit changes all instances where we have a single declared license in the tag as both the before and after are identical in tag contents. There's also a few places where I found we did not have a tag and have introduced one. Signed-off-by: Tom Rini <trini@konsulko.com>
194 lines
3.9 KiB
ArmAsm
194 lines
3.9 KiB
ArmAsm
/* SPDX-License-Identifier: GPL-2.0+ */
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/*
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* Copyright (C) 2007-2008
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* Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
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*
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* Copyright (C) 2007
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* Kenati Technologies, Inc.
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*
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* board/MigoR/lowlevel_init.S
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*/
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#include <config.h>
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#include <asm/processor.h>
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#include <asm/macro.h>
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/*
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* Board specific low level init code, called _very_ early in the
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* startup sequence. Relocation to SDRAM has not happened yet, no
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* stack is available, bss section has not been initialised, etc.
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*
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* (Note: As no stack is available, no subroutines can be called...).
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*/
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.global lowlevel_init
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.text
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.align 2
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lowlevel_init:
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write32 CCR_A, CCR_D ! Address of Cache Control Register
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! Instruction Cache Invalidate
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write32 MMUCR_A, MMUCR_D ! Address of MMU Control Register
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! TI == TLB Invalidate bit
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write32 MSTPCR0_A, MSTPCR0_D ! Address of Power Control Register 0
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write32 MSTPCR2_A, MSTPCR2_D ! Address of Power Control Register 2
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write16 PFC_PULCR_A, PFC_PULCR_D
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write16 PFC_DRVCR_A, PFC_DRVCR_D
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write16 SBSCR_A, SBSCR_D
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write16 PSCR_A, PSCR_D
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write16 RWTCSR_A, RWTCSR_D_1 ! 0xA4520004 (Watchdog Control / Status Register)
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! 0xA507 -> timer_STOP / WDT_CLK = max
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write16 RWTCNT_A, RWTCNT_D ! 0xA4520000 (Watchdog Count Register)
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! 0x5A00 -> Clear
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write16 RWTCSR_A, RWTCSR_D_2 ! 0xA4520004 (Watchdog Control / Status Register)
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! 0xA504 -> timer_STOP / CLK = 500ms
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write32 DLLFRQ_A, DLLFRQ_D ! 20080115
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! 20080115
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write32 FRQCR_A, FRQCR_D ! 0xA4150000 Frequency control register
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! 20080115
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write32 CCR_A, CCR_D_2 ! Address of Cache Control Register
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! ??
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bsc_init:
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write32 CMNCR_A, CMNCR_D
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write32 CS0BCR_A, CS0BCR_D
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write32 CS4BCR_A, CS4BCR_D
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write32 CS5ABCR_A, CS5ABCR_D
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write32 CS5BBCR_A, CS5BBCR_D
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write32 CS6ABCR_A, CS6ABCR_D
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write32 CS0WCR_A, CS0WCR_D
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write32 CS4WCR_A, CS4WCR_D
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write32 CS5AWCR_A, CS5AWCR_D
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write32 CS5BWCR_A, CS5BWCR_D
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write32 CS6AWCR_A, CS6AWCR_D
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! SDRAM initialization
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write32 SDCR_A, SDCR_D
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write32 SDWCR_A, SDWCR_D
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write32 SDPCR_A, SDPCR_D
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write32 RTCOR_A, RTCOR_D
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write32 RTCNT_A, RTCNT_D
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write32 RTCSR_A, RTCSR_D
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write32 RFCR_A, RFCR_D
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write8 SDMR3_A, SDMR3_D
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! BL bit off (init = ON) (?!?)
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stc sr, r0 ! BL bit off(init=ON)
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mov.l SR_MASK_D, r1
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and r1, r0
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ldc r0, sr
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rts
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mov #0, r0
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.align 4
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CCR_A: .long CCR
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MMUCR_A: .long MMUCR
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MSTPCR0_A: .long MSTPCR0
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MSTPCR2_A: .long MSTPCR2
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PFC_PULCR_A: .long PULCR
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PFC_DRVCR_A: .long DRVCR
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SBSCR_A: .long SBSCR
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PSCR_A: .long PSCR
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RWTCSR_A: .long RWTCSR
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RWTCNT_A: .long RWTCNT
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FRQCR_A: .long FRQCR
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PLLCR_A: .long PLLCR
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DLLFRQ_A: .long DLLFRQ
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CCR_D: .long 0x00000800
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CCR_D_2: .long 0x00000103
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MMUCR_D: .long 0x00000004
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MSTPCR0_D: .long 0x00001001
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MSTPCR2_D: .long 0xffffffff
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PFC_PULCR_D: .long 0x6000
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PFC_DRVCR_D: .long 0x0464
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FRQCR_D: .long 0x07033639
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PLLCR_D: .long 0x00005000
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DLLFRQ_D: .long 0x000004F6
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CMNCR_A: .long CMNCR
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CMNCR_D: .long 0x0000001B
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CS0BCR_A: .long CS0BCR
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CS0BCR_D: .long 0x24920400
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CS4BCR_A: .long CS4BCR
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CS4BCR_D: .long 0x00003400
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CS5ABCR_A: .long CS5ABCR
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CS5ABCR_D: .long 0x24920400
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CS5BBCR_A: .long CS5BBCR
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CS5BBCR_D: .long 0x24920400
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CS6ABCR_A: .long CS6ABCR
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CS6ABCR_D: .long 0x24920400
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CS0WCR_A: .long CS0WCR
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CS0WCR_D: .long 0x00000380
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CS4WCR_A: .long CS4WCR
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CS4WCR_D: .long 0x00110080
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CS5AWCR_A: .long CS5AWCR
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CS5AWCR_D: .long 0x00000300
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CS5BWCR_A: .long CS5BWCR
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CS5BWCR_D: .long 0x00000300
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CS6AWCR_A: .long CS6AWCR
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CS6AWCR_D: .long 0x00000300
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SDCR_A: .long SBSC_SDCR
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SDCR_D: .long 0x80160809
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SDWCR_A: .long SBSC_SDWCR
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SDWCR_D: .long 0x0014450C
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SDPCR_A: .long SBSC_SDPCR
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SDPCR_D: .long 0x00000087
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RTCOR_A: .long SBSC_RTCOR
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RTCNT_A: .long SBSC_RTCNT
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RTCNT_D: .long 0xA55A0012
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RTCOR_D: .long 0xA55A001C
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RTCSR_A: .long SBSC_RTCSR
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RFCR_A: .long SBSC_RFCR
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RFCR_D: .long 0xA55A0221
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RTCSR_D: .long 0xA55A009a
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SDMR3_A: .long 0xFE581180
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SDMR3_D: .long 0x0
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SR_MASK_D: .long 0xEFFFFF0F
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.align 2
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SBSCR_D: .word 0x0044
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PSCR_D: .word 0x0000
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RWTCSR_D_1: .word 0xA507
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RWTCSR_D_2: .word 0xA504
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RWTCNT_D: .word 0x5A00
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