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u-boot-megous/drivers/clk
Hoegeun Kwon 422fc299df clk: starfive: pll: Fix to use postdiv1_mask
There is a problem that the rates of PLL0 and PLL1 are set incorrectly
because the postdiv1_mask value is incorrectly entered when setting
the pll clk reg. Modify postdiv1's mask value to be put correctly.

Signed-off-by: Hoegeun Kwon <hoegeun.kwon@samsung.com>
Reviewed-by: Minkyu Kang <mk7.kang@samsung.com>
2023-07-06 17:28:08 +08:00
..
2023-03-06 17:03:56 -05:00
2023-05-13 04:01:30 +02:00
2023-02-09 16:32:25 -05:00
2023-02-10 07:41:40 -05:00