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There is a problem that the rates of PLL0 and PLL1 are set incorrectly because the postdiv1_mask value is incorrectly entered when setting the pll clk reg. Modify postdiv1's mask value to be put correctly. Signed-off-by: Hoegeun Kwon <hoegeun.kwon@samsung.com> Reviewed-by: Minkyu Kang <mk7.kang@samsung.com>