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https://xff.cz/git/u-boot/
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cc4a0ceeac
rename CFG_NAND_LEGACY to CONFIG_NAND_LEGACY Signed-off-by: Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com>
151 lines
3.4 KiB
C
151 lines
3.4 KiB
C
/*
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* FSL UPM NAND driver
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*
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* Copyright (C) 2007 MontaVista Software, Inc.
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* Anton Vorontsov <avorontsov@ru.mvista.com>
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License as
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* published by the Free Software Foundation; either version 2 of
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* the License, or (at your option) any later version.
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*/
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#include <config.h>
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#include <common.h>
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#include <asm/io.h>
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#include <asm/errno.h>
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#include <linux/mtd/mtd.h>
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#include <linux/mtd/fsl_upm.h>
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#include <nand.h>
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static void fsl_upm_start_pattern(struct fsl_upm *upm, u32 pat_offset)
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{
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clrsetbits_be32(upm->mxmr, MxMR_MAD_MSK, MxMR_OP_RUNP | pat_offset);
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}
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static void fsl_upm_end_pattern(struct fsl_upm *upm)
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{
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clrbits_be32(upm->mxmr, MxMR_OP_RUNP);
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while (in_be32(upm->mxmr) & MxMR_OP_RUNP)
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eieio();
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}
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static void fsl_upm_run_pattern(struct fsl_upm *upm, int width, u32 cmd)
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{
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out_be32(upm->mar, cmd << (32 - width));
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switch (width) {
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case 8:
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out_8(upm->io_addr, 0x0);
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break;
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case 16:
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out_be16(upm->io_addr, 0x0);
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break;
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case 32:
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out_be32(upm->io_addr, 0x0);
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break;
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}
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}
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static void fun_cmd_ctrl(struct mtd_info *mtd, int cmd, unsigned int ctrl)
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{
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struct nand_chip *chip = mtd->priv;
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struct fsl_upm_nand *fun = chip->priv;
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if (!(ctrl & fun->last_ctrl)) {
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fsl_upm_end_pattern(&fun->upm);
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if (cmd == NAND_CMD_NONE)
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return;
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fun->last_ctrl = ctrl & (NAND_ALE | NAND_CLE);
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}
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if (ctrl & NAND_CTRL_CHANGE) {
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if (ctrl & NAND_ALE)
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fsl_upm_start_pattern(&fun->upm, fun->upm_addr_offset);
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else if (ctrl & NAND_CLE)
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fsl_upm_start_pattern(&fun->upm, fun->upm_cmd_offset);
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}
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fsl_upm_run_pattern(&fun->upm, fun->width, cmd);
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/*
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* Some boards/chips needs this. At least on MPC8360E-RDK we
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* need it. Probably weird chip, because I don't see any need
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* for this on MPC8555E + Samsung K9F1G08U0A. Usually here are
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* 0-2 unexpected busy states per block read.
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*/
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if (fun->wait_pattern) {
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while (!fun->dev_ready())
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debug("unexpected busy state\n");
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}
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}
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static u8 nand_read_byte(struct mtd_info *mtd)
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{
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struct nand_chip *chip = mtd->priv;
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return in_8(chip->IO_ADDR_R);
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}
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static void nand_write_buf(struct mtd_info *mtd, const u_char *buf, int len)
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{
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int i;
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struct nand_chip *chip = mtd->priv;
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for (i = 0; i < len; i++)
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out_8(chip->IO_ADDR_W, buf[i]);
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}
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static void nand_read_buf(struct mtd_info *mtd, u_char *buf, int len)
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{
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int i;
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struct nand_chip *chip = mtd->priv;
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for (i = 0; i < len; i++)
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buf[i] = in_8(chip->IO_ADDR_R);
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}
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static int nand_verify_buf(struct mtd_info *mtd, const u_char *buf, int len)
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{
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int i;
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struct nand_chip *chip = mtd->priv;
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for (i = 0; i < len; i++) {
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if (buf[i] != in_8(chip->IO_ADDR_R))
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return -EFAULT;
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}
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return 0;
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}
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static int nand_dev_ready(struct mtd_info *mtd)
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{
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struct nand_chip *chip = mtd->priv;
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struct fsl_upm_nand *fun = chip->priv;
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return fun->dev_ready();
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}
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int fsl_upm_nand_init(struct nand_chip *chip, struct fsl_upm_nand *fun)
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{
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if (fun->width != 8 && fun->width != 16 && fun->width != 32)
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return -ENOSYS;
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fun->last_ctrl = NAND_CLE;
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chip->priv = fun;
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chip->chip_delay = fun->chip_delay;
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chip->ecc.mode = NAND_ECC_SOFT;
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chip->cmd_ctrl = fun_cmd_ctrl;
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chip->read_byte = nand_read_byte;
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chip->read_buf = nand_read_buf;
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chip->write_buf = nand_write_buf;
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chip->verify_buf = nand_verify_buf;
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if (fun->dev_ready)
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chip->dev_ready = nand_dev_ready;
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return 0;
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}
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