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af50d92ae7
Fill is code for programming the DDR_PHY_CMD_DESKEW_CONx registers, which are optional, but can be used to fill in the byte lane delays. Signed-off-by: Marek Vasut <marex@denx.de> Cc: Fabio Estevam <festevam@gmail.com> Cc: NXP i.MX U-Boot Team <uboot-imx@nxp.com> Cc: Peng Fan <peng.fan@nxp.com> Cc: Stefano Babic <sbabic@denx.de>
171 lines
4.7 KiB
C
171 lines
4.7 KiB
C
/* SPDX-License-Identifier: GPL-2.0+ */
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/*
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* DDR controller registers of the i.MX7 architecture
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*
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* (C) Copyright 2017 CompuLab, Ltd. http://www.compulab.com
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*
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* Author: Uri Mashiach <uri.mashiach@compulab.co.il>
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*/
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#ifndef __ASM_ARCH_MX7_DDR_H__
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#define __ASM_ARCH_MX7_DDR_H__
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#ifndef __ASSEMBLY__
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#include <linux/bitops.h>
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#endif
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/* DDRC Registers (DDRC_IPS_BASE_ADDR) */
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struct ddrc {
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u32 mstr; /* 0x0000 */
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u32 reserved1[0x18];
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u32 rfshtmg; /* 0x0064 */
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u32 reserved2[0x1a];
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u32 init0; /* 0x00d0 */
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u32 init1; /* 0x00d4 */
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u32 reserved3;
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u32 init3; /* 0x00dc */
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u32 init4; /* 0x00e0 */
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u32 init5; /* 0x00e4 */
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u32 reserved4[0x03];
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u32 rankctl; /* 0x00f4 */
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u32 reserved5[0x02];
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u32 dramtmg0; /* 0x0100 */
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u32 dramtmg1; /* 0x0104 */
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u32 dramtmg2; /* 0x0108 */
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u32 dramtmg3; /* 0x010c */
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u32 dramtmg4; /* 0x0110 */
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u32 dramtmg5; /* 0x0114 */
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u32 reserved6[0x02];
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u32 dramtmg8; /* 0x0120 */
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u32 reserved7[0x17];
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u32 zqctl0; /* 0x0180 */
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u32 zqctl1; /* 0x0184 */
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u32 zqctl2; /* 0x0188 */
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u32 zqstat; /* 0x018c */
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u32 dfitmg0; /* 0x0190 */
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u32 dfitmg1; /* 0x0194 */
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u32 reserved9[0x02];
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u32 dfiupd0; /* 0x01a0 */
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u32 dfiupd1; /* 0x01a4 */
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u32 dfiupd2; /* 0x01a8 */
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u32 reserved10[0x15];
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u32 addrmap0; /* 0x0200 */
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u32 addrmap1; /* 0x0204 */
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u32 addrmap2; /* 0x0208 */
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u32 addrmap3; /* 0x020c */
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u32 addrmap4; /* 0x0210 */
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u32 addrmap5; /* 0x0214 */
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u32 addrmap6; /* 0x0218 */
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u32 reserved12[0x09];
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u32 odtcfg; /* 0x0240 */
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u32 odtmap; /* 0x0244 */
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};
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/* DDRC_MSTR fields */
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#define MSTR_DATA_BUS_WIDTH_MASK 0x3 << 12
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#define MSTR_DATA_BUS_WIDTH_SHIFT 12
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#define MSTR_DATA_ACTIVE_RANKS_MASK 0xf << 24
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#define MSTR_DATA_ACTIVE_RANKS_SHIFT 24
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/* DDRC_ADDRMAP1 fields */
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#define ADDRMAP1_BANK_B0_MASK 0x1f << 0
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#define ADDRMAP1_BANK_B0_SHIFT 0
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#define ADDRMAP1_BANK_B1_MASK 0x1f << 8
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#define ADDRMAP1_BANK_B1_SHIFT 8
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#define ADDRMAP1_BANK_B2_MASK 0x1f << 16
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#define ADDRMAP1_BANK_B2_SHIFT 16
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/* DDRC_ADDRMAP2 fields */
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#define ADDRMAP2_COL_B2_MASK 0xF << 0
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#define ADDRMAP2_COL_B2_SHIFT 0
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#define ADDRMAP2_COL_B3_MASK 0xF << 8
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#define ADDRMAP2_COL_B3_SHIFT 8
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#define ADDRMAP2_COL_B4_MASK 0xF << 16
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#define ADDRMAP2_COL_B4_SHIFT 16
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#define ADDRMAP2_COL_B5_MASK 0xF << 24
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#define ADDRMAP2_COL_B5_SHIFT 24
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/* DDRC_ADDRMAP3 fields */
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#define ADDRMAP3_COL_B6_MASK 0xF << 0
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#define ADDRMAP3_COL_B6_SHIFT 0
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#define ADDRMAP3_COL_B7_MASK 0xF << 8
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#define ADDRMAP3_COL_B7_SHIFT 8
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#define ADDRMAP3_COL_B8_MASK 0xF << 16
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#define ADDRMAP3_COL_B8_SHIFT 16
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#define ADDRMAP3_COL_B9_MASK 0xF << 24
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#define ADDRMAP3_COL_B9_SHIFT 24
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/* DDRC_ADDRMAP4 fields */
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#define ADDRMAP4_COL_B10_MASK 0xF << 0
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#define ADDRMAP4_COL_B10_SHIFT 0
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#define ADDRMAP4_COL_B11_MASK 0xF << 8
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#define ADDRMAP4_COL_B11_SHIFT 8
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/* DDRC_ADDRMAP5 fields */
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#define ADDRMAP5_ROW_B0_MASK 0xF << 0
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#define ADDRMAP5_ROW_B0_SHIFT 0
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#define ADDRMAP5_ROW_B1_MASK 0xF << 8
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#define ADDRMAP5_ROW_B1_SHIFT 8
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#define ADDRMAP5_ROW_B2_10_MASK 0xF << 16
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#define ADDRMAP5_ROW_B2_10_SHIFT 16
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#define ADDRMAP5_ROW_B11_MASK 0xF << 24
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#define ADDRMAP5_ROW_B11_SHIFT 24
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/* DDRC_ADDRMAP6 fields */
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#define ADDRMAP6_ROW_B12_MASK 0xF << 0
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#define ADDRMAP6_ROW_B12_SHIFT 0
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#define ADDRMAP6_ROW_B13_MASK 0xF << 8
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#define ADDRMAP6_ROW_B13_SHIFT 8
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#define ADDRMAP6_ROW_B14_MASK 0xF << 16
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#define ADDRMAP6_ROW_B14_SHIFT 16
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#define ADDRMAP6_ROW_B15_MASK 0xF << 24
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#define ADDRMAP6_ROW_B15_SHIFT 24
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/* DDRC_MP Registers */
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#define DDRC_MP_BASE_ADDR (DDRC_IPS_BASE_ADDR + 0x03fc)
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struct ddrc_mp {
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u32 reserved1[0x25];
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u32 pctrl_0; /* 0x0094 */
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};
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/* DDR_PHY registers */
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struct ddr_phy {
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u32 phy_con0; /* 0x0000 */
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u32 phy_con1; /* 0x0004 */
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u32 reserved1[0x02];
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u32 phy_con4; /* 0x0010 */
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u32 reserved2;
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u32 offset_lp_con0; /* 0x0018 */
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u32 reserved3;
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u32 offset_rd_con0; /* 0x0020 */
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u32 reserved4[0x03];
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u32 offset_wr_con0; /* 0x0030 */
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u32 reserved5[0x07];
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u32 cmd_sdll_con0; /* 0x0050 */
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u32 reserved6[0x06];
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u32 cmd_lvl_con0; /* 0x006c */
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u32 reserved7[0x02];
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u32 cmd_lvl_con3; /* 0x0078 */
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u32 cmd_deskew_con0; /* 0x007c */
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u32 cmd_deskew_con1; /* 0x0080 */
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u32 cmd_deskew_con2; /* 0x0084 */
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u32 cmd_deskew_con3; /* 0x0088 */
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u32 reserved8[0x02];
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u32 cmd_deskew_con4; /* 0x0094 */
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u32 reserved9;
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u32 drvds_con0; /* 0x009c */
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u32 reserved10[0x04];
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u32 mdll_con0; /* 0x00b0 */
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u32 reserved11[0x03];
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u32 zq_con0; /* 0x00c0 */
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};
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#define DDR_PHY_CMD_SDLL_CON0_CTRL_RESYNC_MASK BIT(24)
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#define MX7_CAL_VAL_MAX 5
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/* Calibration parameters */
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struct mx7_calibration {
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int num_val; /* Number of calibration values */
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u32 values[MX7_CAL_VAL_MAX]; /* calibration values */
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};
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void mx7_dram_cfg(struct ddrc *ddrc_regs_val, struct ddrc_mp *ddrc_mp_val,
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struct ddr_phy *ddr_phy_regs_val,
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struct mx7_calibration *calib_param);
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#endif /*__ASM_ARCH_MX7_DDR_H__ */
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