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83d290c56f
When U-Boot started using SPDX tags we were among the early adopters and there weren't a lot of other examples to borrow from. So we picked the area of the file that usually had a full license text and replaced it with an appropriate SPDX-License-Identifier: entry. Since then, the Linux Kernel has adopted SPDX tags and they place it as the very first line in a file (except where shebangs are used, then it's second line) and with slightly different comment styles than us. In part due to community overlap, in part due to better tag visibility and in part for other minor reasons, switch over to that style. This commit changes all instances where we have a single declared license in the tag as both the before and after are identical in tag contents. There's also a few places where I found we did not have a tag and have introduced one. Signed-off-by: Tom Rini <trini@konsulko.com>
117 lines
4.5 KiB
C
117 lines
4.5 KiB
C
/* SPDX-License-Identifier: GPL-2.0+ */
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/*
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* [origin: Linux kernel arch/arm/mach-at91/include/mach/at91_wdt.h]
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*
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* Copyright (C) 2009 Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com>
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* Copyright (C) 2007 Andrew Victor
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* Copyright (C) 2007 Atmel Corporation.
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*
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* SDRAM Controllers (SDRAMC) - System peripherals registers.
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* Based on AT91SAM9261 datasheet revision D.
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*/
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#ifndef AT91SAM9_SDRAMC_H
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#define AT91SAM9_SDRAMC_H
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#ifdef __ASSEMBLY__
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#ifndef ATMEL_BASE_SDRAMC
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#define ATMEL_BASE_SDRAMC ATMEL_BASE_SDRAMC0
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#endif
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#define AT91_ASM_SDRAMC_MR ATMEL_BASE_SDRAMC
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#define AT91_ASM_SDRAMC_TR (ATMEL_BASE_SDRAMC + 0x04)
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#define AT91_ASM_SDRAMC_CR (ATMEL_BASE_SDRAMC + 0x08)
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#define AT91_ASM_SDRAMC_MDR (ATMEL_BASE_SDRAMC + 0x24)
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#else
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struct sdramc_reg {
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u32 mr;
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u32 tr;
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u32 cr;
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u32 lpr;
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u32 ier;
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u32 idr;
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u32 imr;
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u32 isr;
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u32 mdr;
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};
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int sdramc_initialize(unsigned int sdram_address,
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const struct sdramc_reg *p);
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#endif
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/* SDRAM Controller (SDRAMC) registers */
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#define AT91_SDRAMC_MR (ATMEL_BASE_SDRAMC + 0x00) /* SDRAM Controller Mode Register */
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#define AT91_SDRAMC_MODE (0xf << 0) /* Command Mode */
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#define AT91_SDRAMC_MODE_NORMAL 0
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#define AT91_SDRAMC_MODE_NOP 1
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#define AT91_SDRAMC_MODE_PRECHARGE 2
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#define AT91_SDRAMC_MODE_LMR 3
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#define AT91_SDRAMC_MODE_REFRESH 4
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#define AT91_SDRAMC_MODE_EXT_LMR 5
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#define AT91_SDRAMC_MODE_DEEP 6
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#define AT91_SDRAMC_TR (ATMEL_BASE_SDRAMC + 0x04) /* SDRAM Controller Refresh Timer Register */
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#define AT91_SDRAMC_COUNT (0xfff << 0) /* Refresh Timer Counter */
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#define AT91_SDRAMC_CR (ATMEL_BASE_SDRAMC + 0x08) /* SDRAM Controller Configuration Register */
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#define AT91_SDRAMC_NC (3 << 0) /* Number of Column Bits */
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#define AT91_SDRAMC_NC_8 (0 << 0)
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#define AT91_SDRAMC_NC_9 (1 << 0)
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#define AT91_SDRAMC_NC_10 (2 << 0)
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#define AT91_SDRAMC_NC_11 (3 << 0)
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#define AT91_SDRAMC_NR (3 << 2) /* Number of Row Bits */
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#define AT91_SDRAMC_NR_11 (0 << 2)
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#define AT91_SDRAMC_NR_12 (1 << 2)
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#define AT91_SDRAMC_NR_13 (2 << 2)
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#define AT91_SDRAMC_NB (1 << 4) /* Number of Banks */
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#define AT91_SDRAMC_NB_2 (0 << 4)
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#define AT91_SDRAMC_NB_4 (1 << 4)
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#define AT91_SDRAMC_CAS (3 << 5) /* CAS Latency */
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#define AT91_SDRAMC_CAS_1 (1 << 5)
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#define AT91_SDRAMC_CAS_2 (2 << 5)
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#define AT91_SDRAMC_CAS_3 (3 << 5)
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#define AT91_SDRAMC_DBW (1 << 7) /* Data Bus Width */
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#define AT91_SDRAMC_DBW_32 (0 << 7)
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#define AT91_SDRAMC_DBW_16 (1 << 7)
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#define AT91_SDRAMC_TWR (0xf << 8) /* Write Recovery Delay */
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#define AT91_SDRAMC_TWR_VAL(x) (x << 8)
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#define AT91_SDRAMC_TRC (0xf << 12) /* Row Cycle Delay */
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#define AT91_SDRAMC_TRC_VAL(x) (x << 12)
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#define AT91_SDRAMC_TRP (0xf << 16) /* Row Precharge Delay */
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#define AT91_SDRAMC_TRP_VAL(x) (x << 16)
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#define AT91_SDRAMC_TRCD (0xf << 20) /* Row to Column Delay */
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#define AT91_SDRAMC_TRCD_VAL(x) (x << 20)
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#define AT91_SDRAMC_TRAS (0xf << 24) /* Active to Precharge Delay */
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#define AT91_SDRAMC_TRAS_VAL(x) (x << 24)
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#define AT91_SDRAMC_TXSR (0xf << 28) /* Exit Self Refresh to Active Delay */
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#define AT91_SDRAMC_TXSR_VAL(x) (x << 28)
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#define AT91_SDRAMC_LPR (ATMEL_BASE_SDRAMC + 0x10) /* SDRAM Controller Low Power Register */
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#define AT91_SDRAMC_LPCB (3 << 0) /* Low-power Configurations */
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#define AT91_SDRAMC_LPCB_DISABLE 0
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#define AT91_SDRAMC_LPCB_SELF_REFRESH 1
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#define AT91_SDRAMC_LPCB_POWER_DOWN 2
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#define AT91_SDRAMC_LPCB_DEEP_POWER_DOWN 3
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#define AT91_SDRAMC_PASR (7 << 4) /* Partial Array Self Refresh */
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#define AT91_SDRAMC_TCSR (3 << 8) /* Temperature Compensated Self Refresh */
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#define AT91_SDRAMC_DS (3 << 10) /* Drive Strength */
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#define AT91_SDRAMC_TIMEOUT (3 << 12) /* Time to define when Low Power Mode is enabled */
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#define AT91_SDRAMC_TIMEOUT_0_CLK_CYCLES (0 << 12)
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#define AT91_SDRAMC_TIMEOUT_64_CLK_CYCLES (1 << 12)
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#define AT91_SDRAMC_TIMEOUT_128_CLK_CYCLES (2 << 12)
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#define AT91_SDRAMC_IER (ATMEL_BASE_SDRAMC + 0x14) /* SDRAM Controller Interrupt Enable Register */
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#define AT91_SDRAMC_IDR (ATMEL_BASE_SDRAMC + 0x18) /* SDRAM Controller Interrupt Disable Register */
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#define AT91_SDRAMC_IMR (ATMEL_BASE_SDRAMC + 0x1C) /* SDRAM Controller Interrupt Mask Register */
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#define AT91_SDRAMC_ISR (ATMEL_BASE_SDRAMC + 0x20) /* SDRAM Controller Interrupt Status Register */
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#define AT91_SDRAMC_RES (1 << 0) /* Refresh Error Status */
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#define AT91_SDRAMC_MDR (ATMEL_BASE_SDRAMC + 0x24) /* SDRAM Memory Device Register */
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#define AT91_SDRAMC_MD (3 << 0) /* Memory Device Type */
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#define AT91_SDRAMC_MD_SDRAM 0
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#define AT91_SDRAMC_MD_LOW_POWER_SDRAM 1
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#endif
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