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309 lines
7.6 KiB
C
309 lines
7.6 KiB
C
// SPDX-License-Identifier: GPL-2.0+
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/*
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* Intel Broadwell I2S driver
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*
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* Copyright 2019 Google LLC
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*
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* Modified from dc i2s/broadwell/broadwell.c
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*/
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#define LOG_CATEGORY UCLASS_I2S
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#include <common.h>
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#include <dm.h>
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#include <i2s.h>
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#include <log.h>
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#include <time.h>
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#include <asm/io.h>
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#include "broadwell_i2s.h"
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enum {
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BDW_SHIM_START_ADDRESS = 0xfb000,
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BDW_SSP0_START_ADDRESS = 0xfc000,
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BDW_SSP1_START_ADDRESS = 0xfd000,
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};
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struct broadwell_i2s_priv {
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enum frame_sync_rel_timing_t rel_timing;
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enum frame_sync_pol_t sfrm_polarity;
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enum end_transfer_state_t end_transfer_state;
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enum clock_mode_t sclk_mode;
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uint sclk_dummy_stop; /* 0-31 */
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uint sclk_frame_width; /* 1-38 */
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struct i2s_shim_regs *shim;
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struct broadwell_i2s_regs *regs;
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};
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static void init_shim_csr(struct broadwell_i2s_priv *priv)
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{
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/*
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* Select SSP clock
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* Turn off low power clock
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* Set PIO mode
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* Stall DSP core
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*/
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clrsetbits_le32(&priv->shim->csr,
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SHIM_CS_S0IOCS | SHIM_CS_LPCS | SHIM_CS_DCS_MASK,
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SHIM_CS_S1IOCS | SHIM_CS_SBCS_SSP1_24MHZ |
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SHIM_CS_SBCS_SSP0_24MHZ | SHIM_CS_SDPM_PIO_SSP1 |
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SHIM_CS_SDPM_PIO_SSP0 | SHIM_CS_STALL |
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SHIM_CS_DCS_DSP32_AF32);
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}
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static void init_shim_clkctl(struct i2s_uc_priv *uc_priv,
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struct broadwell_i2s_priv *priv)
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{
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u32 clkctl = readl(&priv->shim->clkctl);
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/* Set 24Mhz mclk, prevent local clock gating, enable SSP0 clock */
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clkctl &= SHIM_CLKCTL_RESERVED;
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clkctl |= SHIM_CLKCTL_MCLK_24MHZ | SHIM_CLKCTL_DCPLCG;
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/* Enable requested SSP interface */
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if (uc_priv->id)
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clkctl |= SHIM_CLKCTL_SCOE_SSP1 | SHIM_CLKCTL_SFLCGB_SSP1_CGD;
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else
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clkctl |= SHIM_CLKCTL_SCOE_SSP0 | SHIM_CLKCTL_SFLCGB_SSP0_CGD;
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writel(clkctl, &priv->shim->clkctl);
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}
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static void init_sscr0(struct i2s_uc_priv *uc_priv,
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struct broadwell_i2s_priv *priv)
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{
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u32 sscr0;
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uint scale;
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/* Set data size based on BPS */
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if (uc_priv->bitspersample > 16)
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sscr0 = (uc_priv->bitspersample - 16 - 1) << SSP_SSC0_DSS_SHIFT
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| SSP_SSC0_EDSS;
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else
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sscr0 = (uc_priv->bitspersample - 1) << SSP_SSC0_DSS_SHIFT;
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/* Set network mode, Stereo PSP frame format */
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sscr0 |= SSP_SSC0_MODE_NETWORK |
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SSP_SSC0_FRDC_STEREO |
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SSP_SSC0_FRF_PSP |
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SSP_SSC0_TIM |
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SSP_SSC0_RIM |
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SSP_SSC0_ECS_PCH |
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SSP_SSC0_NCS_PCH |
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SSP_SSC0_ACS_PCH;
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/* Scale 24MHz MCLK */
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scale = uc_priv->audio_pll_clk / uc_priv->samplingrate / uc_priv->bfs;
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sscr0 |= scale << SSP_SSC0_SCR_SHIFT;
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writel(sscr0, &priv->regs->sscr0);
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}
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static void init_sscr1(struct broadwell_i2s_priv *priv)
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{
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u32 sscr1 = readl(&priv->regs->sscr1);
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sscr1 &= SSP_SSC1_RESERVED;
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/* Set as I2S master */
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sscr1 |= SSP_SSC1_SCLKDIR_MASTER | SSP_SSC1_SCLKDIR_MASTER;
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/* Enable TXD tristate behavior for PCH */
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sscr1 |= SSP_SSC1_TTELP | SSP_SSC1_TTE;
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/* Disable DMA Tx/Rx service request */
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sscr1 |= SSP_SSC1_TSRE | SSP_SSC1_RSRE;
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/* Clock on during transfer */
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sscr1 |= SSP_SSC1_SCFR;
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/* Set FIFO thresholds */
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sscr1 |= SSP_FIFO_SIZE << SSP_SSC1_RFT_SHIFT;
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sscr1 |= SSP_FIFO_SIZE << SSP_SSC1_TFT_SHIFT;
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/* Disable interrupts */
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sscr1 &= ~(SSP_SSC1_EBCEI | SSP_SSC1_TINTE | SSP_SSC1_PINTE);
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sscr1 &= ~(SSP_SSC1_LBM | SSP_SSC1_RWOT);
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writel(sscr1, &priv->regs->sscr1);
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}
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static void init_sspsp(struct broadwell_i2s_priv *priv)
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{
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u32 sspsp = readl(&priv->regs->sspsp);
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sspsp &= SSP_PSP_RESERVED;
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sspsp |= priv->sclk_mode << SSP_PSP_SCMODE_SHIFT;
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sspsp |= (priv->sclk_dummy_stop << SSP_PSP_DMYSTOP_SHIFT) &
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SSP_PSP_DMYSTOP_MASK;
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sspsp |= (priv->sclk_dummy_stop >> 2 << SSP_PSP_EDYMSTOP_SHIFT) &
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SSP_PSP_EDMYSTOP_MASK;
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sspsp |= priv->sclk_frame_width << SSP_PSP_SFRMWDTH_SHIFT;
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/* Frame Sync Relative Timing */
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if (priv->rel_timing == NEXT_FRMS_AFTER_END_OF_T4)
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sspsp |= SSP_PSP_FSRT;
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else
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sspsp &= ~SSP_PSP_FSRT;
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/* Serial Frame Polarity */
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if (priv->sfrm_polarity == SSP_FRMS_ACTIVE_HIGH)
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sspsp |= SSP_PSP_SFRMP;
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else
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sspsp &= ~SSP_PSP_SFRMP;
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/* End Data Transfer State */
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if (priv->end_transfer_state == SSP_END_TRANSFER_STATE_LOW)
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sspsp &= ~SSP_PSP_ETDS;
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else
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sspsp |= SSP_PSP_ETDS;
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writel(sspsp, &priv->regs->sspsp);
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}
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static void init_ssp_time_slot(struct broadwell_i2s_priv *priv)
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{
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writel(3, &priv->regs->sstsa);
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writel(3, &priv->regs->ssrsa);
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}
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static int bdw_i2s_init(struct udevice *dev)
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{
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struct i2s_uc_priv *uc_priv = dev_get_uclass_priv(dev);
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struct broadwell_i2s_priv *priv = dev_get_priv(dev);
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init_shim_csr(priv);
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init_shim_clkctl(uc_priv, priv);
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init_sscr0(uc_priv, priv);
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init_sscr1(priv);
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init_sspsp(priv);
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init_ssp_time_slot(priv);
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return 0;
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}
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static void bdw_i2s_enable(struct broadwell_i2s_priv *priv)
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{
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setbits_le32(&priv->regs->sscr0, SSP_SSC0_SSE);
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setbits_le32(&priv->regs->sstsa, SSP_SSTSA_EN);
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}
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static void bdw_i2s_disable(struct broadwell_i2s_priv *priv)
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{
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clrbits_le32(&priv->regs->sstsa, SSP_SSTSA_EN);
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clrbits_le32(&priv->regs->sstsa, SSP_SSTSA_EN);
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}
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static int broadwell_i2s_tx_data(struct udevice *dev, void *data,
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uint data_size)
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{
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struct broadwell_i2s_priv *priv = dev_get_priv(dev);
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u32 *ptr = data;
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log_debug("data=%p, data_size=%x\n", data, data_size);
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if (data_size < SSP_FIFO_SIZE) {
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log_err("Invalid I2S data size\n");
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return -ENODATA;
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}
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/* Enable I2S interface */
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bdw_i2s_enable(priv);
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/* Transfer data */
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while (data_size > 0) {
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ulong start = timer_get_us() + 100000;
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/* Write data if transmit FIFO has room */
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if (readl(&priv->regs->sssr) & SSP_SSS_TNF) {
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writel(*ptr++, &priv->regs->ssdr);
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data_size -= sizeof(*ptr);
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} else {
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if ((long)(timer_get_us() - start) > 0) {
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/* Disable I2S interface */
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bdw_i2s_disable(priv);
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log_debug("I2S Transfer Timeout\n");
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return -ETIMEDOUT;
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}
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}
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}
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/* Disable I2S interface */
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bdw_i2s_disable(priv);
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log_debug("done\n");
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return 0;
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}
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static int broadwell_i2s_probe(struct udevice *dev)
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{
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struct i2s_uc_priv *uc_priv = dev_get_uclass_priv(dev);
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struct broadwell_i2s_priv *priv = dev_get_priv(dev);
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struct udevice *adsp = dev_get_parent(dev);
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u32 bar0, offset;
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int ret;
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bar0 = dm_pci_read_bar32(adsp, 0);
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if (!bar0) {
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log_debug("Cannot read adsp bar0\n");
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return -EINVAL;
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}
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offset = dev_read_addr_index(dev, 0);
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if (offset == FDT_ADDR_T_NONE) {
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log_debug("Cannot read address index 0\n");
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return -EINVAL;
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}
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uc_priv->base_address = bar0 + offset;
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/*
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* Hard-code these values. If other settings are required we can add
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* this to the device tree.
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*/
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uc_priv->rfs = 64;
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uc_priv->bfs = 32;
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uc_priv->audio_pll_clk = 24 * 1000 * 1000;
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uc_priv->samplingrate = 48000;
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uc_priv->bitspersample = 16;
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uc_priv->channels = 2;
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uc_priv->id = 0;
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priv->shim = (struct i2s_shim_regs *)uc_priv->base_address;
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priv->sfrm_polarity = SSP_FRMS_ACTIVE_LOW;
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priv->end_transfer_state = SSP_END_TRANSFER_STATE_LOW;
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priv->sclk_mode = SCLK_MODE_DDF_DSR_ISL;
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priv->rel_timing = NEXT_FRMS_WITH_LSB_PREVIOUS_FRM;
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priv->sclk_dummy_stop = 0;
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priv->sclk_frame_width = 31;
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offset = dev_read_addr_index(dev, 1 + uc_priv->id);
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if (offset == FDT_ADDR_T_NONE) {
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log_debug("Cannot read address index %d\n", 1 + uc_priv->id);
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return -EINVAL;
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}
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log_debug("bar0=%x, uc_priv->base_address=%x, offset=%x\n", bar0,
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uc_priv->base_address, offset);
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priv->regs = (struct broadwell_i2s_regs *)(bar0 + offset);
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ret = bdw_i2s_init(dev);
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if (ret)
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return ret;
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return 0;
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}
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static const struct i2s_ops broadwell_i2s_ops = {
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.tx_data = broadwell_i2s_tx_data,
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};
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static const struct udevice_id broadwell_i2s_ids[] = {
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{ .compatible = "intel,broadwell-i2s" },
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{ }
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};
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U_BOOT_DRIVER(broadwell_i2s) = {
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.name = "broadwell_i2s",
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.id = UCLASS_I2S,
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.of_match = broadwell_i2s_ids,
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.probe = broadwell_i2s_probe,
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.ops = &broadwell_i2s_ops,
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.priv_auto_alloc_size = sizeof(struct broadwell_i2s_priv),
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};
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