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cad7b6b251
This cannot be used since the previous #elif has already dealt with SPL. Drop it. Signed-off-by: Simon Glass <sjg@chromium.org>
182 lines
3.0 KiB
Plaintext
182 lines
3.0 KiB
Plaintext
// SPDX-License-Identifier: GPL-2.0+
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/*
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* Copyright (C) 2016 Google, Inc
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* Written by Simon Glass <sjg@chromium.org>
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*/
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#include <config.h>
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/ {
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binman {
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multiple-images;
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rom: rom {
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};
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};
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};
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#ifdef CONFIG_ROM_SIZE
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&rom {
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filename = "u-boot.rom";
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end-at-4gb;
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sort-by-offset;
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pad-byte = <0xff>;
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size = <CONFIG_ROM_SIZE>;
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#ifdef CONFIG_HAVE_INTEL_ME
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intel-descriptor {
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filename = CONFIG_FLASH_DESCRIPTOR_FILE;
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};
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intel-me {
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filename = CONFIG_INTEL_ME_FILE;
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};
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#endif
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#ifdef CONFIG_TPL
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#ifdef CONFIG_HAVE_MICROCODE
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u-boot-tpl-with-ucode-ptr {
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offset = <CONFIG_TPL_TEXT_BASE>;
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};
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u-boot-tpl-dtb {
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};
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#endif
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spl {
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type = "u-boot-spl";
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offset = <CONFIG_X86_OFFSET_SPL>;
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};
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u-boot {
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offset = <CONFIG_X86_OFFSET_U_BOOT>;
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};
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#elif defined(CONFIG_SPL)
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u-boot-spl-with-ucode-ptr {
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offset = <CONFIG_X86_OFFSET_SPL>;
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};
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u-boot-dtb-with-ucode2 {
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type = "u-boot-dtb-with-ucode";
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};
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u-boot {
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offset = <CONFIG_X86_OFFSET_U_BOOT>;
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};
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#else
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# ifdef CONFIG_HAVE_MICROCODE
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/* If there is no SPL then we need to put microcode in U-Boot */
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u-boot-with-ucode-ptr {
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offset = <CONFIG_X86_OFFSET_U_BOOT>;
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};
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# else
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u-boot-nodtb {
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offset = <CONFIG_X86_OFFSET_U_BOOT>;
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};
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# endif
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#endif
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#ifdef CONFIG_HAVE_MICROCODE
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u-boot-dtb-with-ucode {
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};
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u-boot-ucode {
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align = <16>;
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};
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#else
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u-boot-dtb {
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};
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#endif
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fdtmap {
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};
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#ifdef CONFIG_HAVE_X86_FIT
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intel-fit {
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};
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intel-fit-ptr {
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};
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#endif
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#ifdef CONFIG_HAVE_MRC
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intel-mrc {
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offset = <CONFIG_X86_MRC_ADDR>;
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};
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#endif
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#ifdef CONFIG_FSP_VERSION1
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intel-fsp {
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filename = CONFIG_FSP_FILE;
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offset = <CONFIG_FSP_ADDR>;
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};
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#endif
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#ifdef CONFIG_FSP_VERSION2
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intel-descriptor {
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filename = CONFIG_FLASH_DESCRIPTOR_FILE;
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};
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intel-ifwi {
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filename = CONFIG_IFWI_INPUT_FILE;
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convert-fit;
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section {
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size = <0x8000>;
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ifwi-replace;
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ifwi-subpart = "IBBP";
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ifwi-entry = "IBBL";
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u-boot-tpl {
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};
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x86-start16-tpl {
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offset = <0x7800>;
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};
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x86-reset16-tpl {
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offset = <0x7ff0>;
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};
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};
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};
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intel-fsp-m {
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filename = CONFIG_FSP_FILE_M;
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};
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intel-fsp-s {
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filename = CONFIG_FSP_FILE_S;
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};
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#endif
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private_files: private-files {
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type = "files";
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pattern = "*.dat";
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};
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#ifdef CONFIG_HAVE_CMC
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intel-cmc {
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filename = CONFIG_CMC_FILE;
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offset = <CONFIG_CMC_ADDR>;
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};
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#endif
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#ifdef CONFIG_HAVE_VGA_BIOS
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intel-vga {
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filename = CONFIG_VGA_BIOS_FILE;
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offset = <CONFIG_VGA_BIOS_ADDR>;
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};
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#endif
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#ifdef CONFIG_HAVE_VBT
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intel-vbt {
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filename = CONFIG_VBT_FILE;
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offset = <CONFIG_VBT_ADDR>;
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};
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#endif
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#ifdef CONFIG_HAVE_REFCODE
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intel-refcode {
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offset = <CONFIG_X86_REFCODE_ADDR>;
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};
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#endif
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#ifdef CONFIG_TPL
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x86-start16-tpl {
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offset = <CONFIG_SYS_X86_START16>;
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};
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x86-reset16-tpl {
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offset = <CONFIG_RESET_VEC_LOC>;
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};
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#elif defined(CONFIG_SPL)
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x86-start16-spl {
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offset = <CONFIG_SYS_X86_START16>;
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};
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x86-reset16-spl {
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offset = <CONFIG_RESET_VEC_LOC>;
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};
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#else
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x86-start16 {
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offset = <CONFIG_SYS_X86_START16>;
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};
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x86-reset16 {
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offset = <CONFIG_RESET_VEC_LOC>;
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};
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#endif
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image-header {
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location = "end";
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};
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};
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#endif
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