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41cada4d24
Previous SLC management implementation is broken. Seems like it was never sufficiently tested probably because most of the time IOC was used instead (i.e. no manual cache operations were done). Now if we disable IOC in U-boot we'll get a lot of errors while using DMA-enabled peripherals. This time we fix it by substitution of broken per-line SLC operations region operations as it is done in the Linux kernel (we took it from v4.14 which is the latest stable as of today). Among other things this implementation might be a bit faster because instead of iteration over each and every cache line we're taking care about entire region in one go. Main changes: * Replaced __slc_line_op (per line operations) by __slc_rgn_op (region operations). * Reworked __slc_entire_op to get rid of __after_slc_op and __before_slc_op functions. Note flush fix (flush only instead of flush-n-inv when OP_FLUSH is used, see [1] for more details) is already incorporated here. * Added SLC invalidation to invalidate_icache_all(). * Added (start >= end) check to invalidate_dcache_range() and flush_dcache_range() as some buggy drivers pass region start == end. * Added read-out of MMU BCR so we may know if PAE40 exists in HW and then act on a particular AUX regs accordingly. [1] http://lists.infradead.org/pipermail/linux-snps-arc/2018-January/003357.html Signed-off-by: Eugeniy Paltsev <Eugeniy.Paltsev@synopsys.com> Signed-off-by: Alexey Brodkin <abrodkin@synopsys.com>
94 lines
2.7 KiB
C
94 lines
2.7 KiB
C
/*
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* Copyright (C) 2004, 2007-2010, 2011-2012 Synopsys, Inc. All rights reserved.
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*
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* SPDX-License-Identifier: GPL-2.0+
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*/
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#ifndef _ASM_ARC_ARCREGS_H
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#define _ASM_ARC_ARCREGS_H
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#include <asm/cache.h>
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/*
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* ARC architecture has additional address space - auxiliary registers.
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* These registers are mostly used for configuration purposes.
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* These registers are not memory mapped and special commands are used for
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* access: "lr"/"sr".
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*/
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#define ARC_AUX_IDENTITY 0x04
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#define ARC_AUX_STATUS32 0x0a
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/* Instruction cache related auxiliary registers */
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#define ARC_AUX_IC_IVIC 0x10
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#define ARC_AUX_IC_CTRL 0x11
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#define ARC_AUX_IC_IVIL 0x19
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#if (CONFIG_ARC_MMU_VER == 3)
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#define ARC_AUX_IC_PTAG 0x1E
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#endif
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#define ARC_BCR_IC_BUILD 0x77
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#define AUX_AUX_CACHE_LIMIT 0x5D
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#define ARC_AUX_NON_VOLATILE_LIMIT 0x5E
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/* ICCM and DCCM auxiliary registers */
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#define ARC_AUX_DCCM_BASE 0x18 /* DCCM Base Addr ARCv2 */
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#define ARC_AUX_ICCM_BASE 0x208 /* ICCM Base Addr ARCv2 */
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/* Timer related auxiliary registers */
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#define ARC_AUX_TIMER0_CNT 0x21 /* Timer 0 count */
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#define ARC_AUX_TIMER0_CTRL 0x22 /* Timer 0 control */
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#define ARC_AUX_TIMER0_LIMIT 0x23 /* Timer 0 limit */
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#define ARC_AUX_TIMER1_CNT 0x100 /* Timer 1 count */
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#define ARC_AUX_TIMER1_CTRL 0x101 /* Timer 1 control */
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#define ARC_AUX_TIMER1_LIMIT 0x102 /* Timer 1 limit */
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#define ARC_AUX_INTR_VEC_BASE 0x25
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/* Data cache related auxiliary registers */
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#define ARC_AUX_DC_IVDC 0x47
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#define ARC_AUX_DC_CTRL 0x48
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#define ARC_AUX_DC_IVDL 0x4A
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#define ARC_AUX_DC_FLSH 0x4B
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#define ARC_AUX_DC_FLDL 0x4C
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#if (CONFIG_ARC_MMU_VER == 3)
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#define ARC_AUX_DC_PTAG 0x5C
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#endif
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#define ARC_BCR_DC_BUILD 0x72
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#define ARC_BCR_SLC 0xce
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#define ARC_AUX_SLC_CONFIG 0x901
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#define ARC_AUX_SLC_CTRL 0x903
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#define ARC_AUX_SLC_FLUSH 0x904
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#define ARC_AUX_SLC_INVALIDATE 0x905
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#define ARC_AUX_SLC_IVDL 0x910
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#define ARC_AUX_SLC_FLDL 0x912
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#define ARC_AUX_SLC_RGN_START 0x914
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#define ARC_AUX_SLC_RGN_START1 0x915
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#define ARC_AUX_SLC_RGN_END 0x916
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#define ARC_AUX_SLC_RGN_END1 0x917
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#define ARC_BCR_CLUSTER 0xcf
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/* MMU Management regs */
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#define ARC_AUX_MMU_BCR 0x06f
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/* IO coherency related auxiliary registers */
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#define ARC_AUX_IO_COH_ENABLE 0x500
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#define ARC_AUX_IO_COH_PARTIAL 0x501
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#define ARC_AUX_IO_COH_AP0_BASE 0x508
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#define ARC_AUX_IO_COH_AP0_SIZE 0x509
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#ifndef __ASSEMBLY__
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/* Accessors for auxiliary registers */
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#define read_aux_reg(reg) __builtin_arc_lr(reg)
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/* gcc builtin sr needs reg param to be long immediate */
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#define write_aux_reg(reg_immed, val) \
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__builtin_arc_sr((unsigned int)val, reg_immed)
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/* ARCNUM [15:8] - field to identify each core in a multi-core system */
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#define CPU_ID_GET() ((read_aux_reg(ARC_AUX_IDENTITY) & 0xFF00) >> 8)
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#endif /* __ASSEMBLY__ */
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#endif /* _ASM_ARC_ARCREGS_H */
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