Paul Barker aecd69879d
clk: renesas: Confirm all clock & reset changes on RZ/G2L ...
When enabling/disabling a clock or reset signal, confirm that the change
has completed before returning from the function. A somewhat arbitrary
100ms timeout is defined to ensure that the system doesn't lock up in
the case of an error.
Since we need to dynamically determine if we're waiting for a 0 bit or a
1 bit, it's easier to use wait_for_bit_32() than readl_poll_timeout().
This change is needed for reliable initialization of the I2C driver
which is added in a following patch.
Signed-off-by: Paul Barker <paul.barker.ct@bp.renesas.com >
Reviewed-by: Marek Vasut <marek.vasut+renesas@mailbox.org >
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aecd69879d