mirror of
https://xff.cz/git/u-boot/
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de77811589
Restructure clock manager driver in the preparation to support A10. Move the Gen5 specific code to _gen5 files. - Change all uint32_t to u32 and change to use macro BIT(n) for bit shift. - Check return value from wait_for_bit(). So change return type to int for cm_write_with_phase() and cm_basic_init(). Signed-off-by: Ley Foon Tan <ley.foon.tan@intel.com>
323 lines
10 KiB
C
323 lines
10 KiB
C
/*
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* Copyright (C) 2013-2017 Altera Corporation <www.altera.com>
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*
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* SPDX-License-Identifier: GPL-2.0+
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*/
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#ifndef _CLOCK_MANAGER_GEN5_H_
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#define _CLOCK_MANAGER_GEN5_H_
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#ifndef __ASSEMBLER__
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struct cm_config {
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/* main group */
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u32 main_vco_base;
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u32 mpuclk;
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u32 mainclk;
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u32 dbgatclk;
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u32 mainqspiclk;
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u32 mainnandsdmmcclk;
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u32 cfg2fuser0clk;
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u32 maindiv;
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u32 dbgdiv;
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u32 tracediv;
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u32 l4src;
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/* peripheral group */
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u32 peri_vco_base;
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u32 emac0clk;
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u32 emac1clk;
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u32 perqspiclk;
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u32 pernandsdmmcclk;
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u32 perbaseclk;
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u32 s2fuser1clk;
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u32 perdiv;
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u32 gpiodiv;
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u32 persrc;
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/* sdram pll group */
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u32 sdram_vco_base;
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u32 ddrdqsclk;
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u32 ddr2xdqsclk;
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u32 ddrdqclk;
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u32 s2fuser2clk;
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/* altera group */
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u32 altera_grp_mpuclk;
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};
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struct socfpga_clock_manager_main_pll {
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u32 vco;
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u32 misc;
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u32 mpuclk;
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u32 mainclk;
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u32 dbgatclk;
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u32 mainqspiclk;
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u32 mainnandsdmmcclk;
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u32 cfgs2fuser0clk;
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u32 en;
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u32 maindiv;
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u32 dbgdiv;
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u32 tracediv;
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u32 l4src;
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u32 stat;
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u32 _pad_0x38_0x40[2];
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};
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struct socfpga_clock_manager_per_pll {
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u32 vco;
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u32 misc;
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u32 emac0clk;
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u32 emac1clk;
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u32 perqspiclk;
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u32 pernandsdmmcclk;
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u32 perbaseclk;
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u32 s2fuser1clk;
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u32 en;
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u32 div;
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u32 gpiodiv;
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u32 src;
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u32 stat;
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u32 _pad_0x34_0x40[3];
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};
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struct socfpga_clock_manager_sdr_pll {
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u32 vco;
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u32 ctrl;
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u32 ddrdqsclk;
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u32 ddr2xdqsclk;
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u32 ddrdqclk;
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u32 s2fuser2clk;
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u32 en;
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u32 stat;
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};
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struct socfpga_clock_manager_altera {
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u32 mpuclk;
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u32 mainclk;
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};
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struct socfpga_clock_manager {
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u32 ctrl;
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u32 bypass;
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u32 inter;
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u32 intren;
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u32 dbctrl;
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u32 stat;
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u32 _pad_0x18_0x3f[10];
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struct socfpga_clock_manager_main_pll main_pll;
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struct socfpga_clock_manager_per_pll per_pll;
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struct socfpga_clock_manager_sdr_pll sdr_pll;
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struct socfpga_clock_manager_altera altera;
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u32 _pad_0xe8_0x200[70];
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};
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/* Clock speed accessors */
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unsigned long cm_get_mpu_clk_hz(void);
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unsigned long cm_get_sdram_clk_hz(void);
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unsigned int cm_get_l4_sp_clk_hz(void);
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unsigned int cm_get_mmc_controller_clk_hz(void);
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unsigned int cm_get_qspi_controller_clk_hz(void);
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unsigned int cm_get_spi_controller_clk_hz(void);
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const unsigned int cm_get_osc_clk_hz(const int osc);
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const unsigned int cm_get_f2s_per_ref_clk_hz(void);
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const unsigned int cm_get_f2s_sdr_ref_clk_hz(void);
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/* Clock configuration accessors */
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int cm_basic_init(const struct cm_config * const cfg);
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const struct cm_config * const cm_get_default_config(void);
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#endif /* __ASSEMBLER__ */
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#define LOCKED_MASK \
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(CLKMGR_INTER_SDRPLLLOCKED_MASK | \
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CLKMGR_INTER_PERPLLLOCKED_MASK | \
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CLKMGR_INTER_MAINPLLLOCKED_MASK)
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#define CLKMGR_CTRL_SAFEMODE BIT(0)
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#define CLKMGR_CTRL_SAFEMODE_OFFSET 0
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#define CLKMGR_BYPASS_PERPLLSRC BIT(4)
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#define CLKMGR_BYPASS_PERPLLSRC_OFFSET 4
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#define CLKMGR_BYPASS_PERPLL BIT(3)
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#define CLKMGR_BYPASS_PERPLL_OFFSET 3
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#define CLKMGR_BYPASS_SDRPLLSRC BIT(2)
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#define CLKMGR_BYPASS_SDRPLLSRC_OFFSET 2
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#define CLKMGR_BYPASS_SDRPLL BIT(1)
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#define CLKMGR_BYPASS_SDRPLL_OFFSET 1
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#define CLKMGR_BYPASS_MAINPLL BIT(0)
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#define CLKMGR_BYPASS_MAINPLL_OFFSET 0
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#define CLKMGR_INTER_MAINPLLLOST_MASK BIT(3)
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#define CLKMGR_INTER_PERPLLLOST_MASK BIT(4)
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#define CLKMGR_INTER_SDRPLLLOST_MASK BIT(5)
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#define CLKMGR_INTER_MAINPLLLOCKED_MASK BIT(6)
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#define CLKMGR_INTER_PERPLLLOCKED_MASK BIT(7)
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#define CLKMGR_INTER_SDRPLLLOCKED_MASK BIT(8)
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#define CLKMGR_STAT_BUSY BIT(0)
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/* Main PLL */
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#define CLKMGR_MAINPLLGRP_VCO_BGPWRDN BIT(0)
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#define CLKMGR_MAINPLLGRP_VCO_BGPWRDN_OFFSET 0
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#define CLKMGR_MAINPLLGRP_VCO_DENOM_OFFSET 16
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#define CLKMGR_MAINPLLGRP_VCO_DENOM_MASK 0x003f0000
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#define CLKMGR_MAINPLLGRP_VCO_EN BIT(1)
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#define CLKMGR_MAINPLLGRP_VCO_EN_OFFSET 1
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#define CLKMGR_MAINPLLGRP_VCO_NUMER_OFFSET 3
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#define CLKMGR_MAINPLLGRP_VCO_NUMER_MASK 0x0000fff8
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#define CLKMGR_MAINPLLGRP_VCO_OUTRESETALL_MASK 0x01000000
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#define CLKMGR_MAINPLLGRP_VCO_PWRDN BIT(2)
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#define CLKMGR_MAINPLLGRP_VCO_PWRDN_OFFSET 2
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#define CLKMGR_MAINPLLGRP_VCO_REGEXTSEL_MASK 0x80000000
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#define CLKMGR_MAINPLLGRP_VCO_RESET_VALUE 0x8001000d
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#define CLKMGR_MAINPLLGRP_MPUCLK_CNT_OFFSET 0
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#define CLKMGR_MAINPLLGRP_MPUCLK_CNT_MASK 0x000001ff
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#define CLKMGR_MAINPLLGRP_MAINCLK_CNT_OFFSET 0
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#define CLKMGR_MAINPLLGRP_MAINCLK_CNT_MASK 0x000001ff
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#define CLKMGR_MAINPLLGRP_DBGATCLK_CNT_OFFSET 0
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#define CLKMGR_MAINPLLGRP_DBGATCLK_CNT_MASK 0x000001ff
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#define CLKMGR_MAINPLLGRP_MAINQSPICLK_CNT_OFFSET 0
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#define CLKMGR_MAINPLLGRP_MAINQSPICLK_CNT_MASK 0x000001ff
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#define CLKMGR_MAINPLLGRP_MAINNANDSDMMCCLK_CNT_OFFSET 0
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#define CLKMGR_MAINPLLGRP_MAINNANDSDMMCCLK_CNT_MASK 0x000001ff
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#define CLKMGR_MAINPLLGRP_CFGS2FUSER0CLK_CNT_OFFSET 0
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#define CLKMGR_MAINPLLGRP_CFGS2FUSER0CLK_CNT_MASK 0x000001ff
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#define CLKMGR_MAINPLLGRP_EN_L4MPCLK_MASK BIT(2)
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#define CLKMGR_MAINPLLGRP_EN_DBGATCLK_MASK BIT(4)
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#define CLKMGR_MAINPLLGRP_EN_DBGCLK_MASK BIT(5)
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#define CLKMGR_MAINPLLGRP_EN_DBGTRACECLK_MASK BIT(6)
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#define CLKMGR_MAINPLLGRP_EN_DBGTIMERCLK_MASK BIT(7)
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#define CLKMGR_MAINPLLGRP_EN_S2FUSER0CLK_MASK BIT(9)
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#define CLKMGR_MAINPLLGRP_MAINDIV_L3MPCLK_OFFSET 0
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#define CLKMGR_MAINPLLGRP_MAINDIV_L3MPCLK_MASK 0x00000003
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#define CLKMGR_MAINPLLGRP_MAINDIV_L3SPCLK_OFFSET 2
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#define CLKMGR_MAINPLLGRP_MAINDIV_L3SPCLK_MASK 0x0000000c
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#define CLKMGR_MAINPLLGRP_MAINDIV_L4MPCLK_OFFSET 4
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#define CLKMGR_MAINPLLGRP_MAINDIV_L4MPCLK_MASK 0x00000070
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#define CLKMGR_MAINPLLGRP_MAINDIV_L4SPCLK_OFFSET 7
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#define CLKMGR_MAINPLLGRP_MAINDIV_L4SPCLK_MASK 0x00000380
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#define CLKMGR_MAINPLLGRP_DBGDIV_DBGATCLK_OFFSET 0
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#define CLKMGR_MAINPLLGRP_DBGDIV_DBGATCLK_MASK 0x00000003
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#define CLKMGR_MAINPLLGRP_DBGDIV_DBGCLK_OFFSET 2
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#define CLKMGR_MAINPLLGRP_DBGDIV_DBGCLK_MASK 0x0000000c
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#define CLKMGR_MAINPLLGRP_TRACEDIV_TRACECLK_OFFSET 0
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#define CLKMGR_MAINPLLGRP_TRACEDIV_TRACECLK_MASK 0x00000007
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#define CLKMGR_MAINPLLGRP_L4SRC_L4MP BIT(0)
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#define CLKMGR_MAINPLLGRP_L4SRC_L4MP_OFFSET 0
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#define CLKMGR_MAINPLLGRP_L4SRC_L4SP BIT(1)
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#define CLKMGR_MAINPLLGRP_L4SRC_L4SP_OFFSET 1
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#define CLKMGR_MAINPLLGRP_L4SRC_RESET_VALUE 0x00000000
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#define CLKMGR_L4_SP_CLK_SRC_MAINPLL 0x0
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#define CLKMGR_L4_SP_CLK_SRC_PERPLL 0x1
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/* Per PLL */
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#define CLKMGR_PERPLLGRP_VCO_DENOM_OFFSET 16
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#define CLKMGR_PERPLLGRP_VCO_DENOM_MASK 0x003f0000
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#define CLKMGR_PERPLLGRP_VCO_NUMER_OFFSET 3
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#define CLKMGR_PERPLLGRP_VCO_NUMER_MASK 0x0000fff8
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#define CLKMGR_PERPLLGRP_VCO_OUTRESETALL_MASK 0x01000000
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#define CLKMGR_PERPLLGRP_VCO_PSRC_OFFSET 22
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#define CLKMGR_PERPLLGRP_VCO_PSRC_MASK 0x00c00000
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#define CLKMGR_PERPLLGRP_VCO_REGEXTSEL_MASK 0x80000000
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#define CLKMGR_PERPLLGRP_VCO_RESET_VALUE 0x8001000d
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#define CLKMGR_PERPLLGRP_VCO_SSRC_OFFSET 22
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#define CLKMGR_PERPLLGRP_VCO_SSRC_MASK 0x00c00000
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#define CLKMGR_VCO_SSRC_EOSC1 0x0
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#define CLKMGR_VCO_SSRC_EOSC2 0x1
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#define CLKMGR_VCO_SSRC_F2S 0x2
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#define CLKMGR_PERPLLGRP_EMAC0CLK_CNT_OFFSET 0
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#define CLKMGR_PERPLLGRP_EMAC0CLK_CNT_MASK 0x000001ff
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#define CLKMGR_PERPLLGRP_EMAC1CLK_CNT_OFFSET 0
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#define CLKMGR_PERPLLGRP_EMAC1CLK_CNT_MASK 0x000001ff
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#define CLKMGR_PERPLLGRP_PERQSPICLK_CNT_OFFSET 0
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#define CLKMGR_PERPLLGRP_PERQSPICLK_CNT_MASK 0x000001ff
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#define CLKMGR_PERPLLGRP_PERNANDSDMMCCLK_CNT_OFFSET 0
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#define CLKMGR_PERPLLGRP_PERNANDSDMMCCLK_CNT_MASK 0x000001ff
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#define CLKMGR_PERPLLGRP_PERBASECLK_CNT_OFFSET 0
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#define CLKMGR_PERPLLGRP_PERBASECLK_CNT_MASK 0x000001ff
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#define CLKMGR_PERPLLGRP_S2FUSER1CLK_CNT_OFFSET 0
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#define CLKMGR_PERPLLGRP_S2FUSER1CLK_CNT_MASK 0x000001ff
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#define CLKMGR_PERPLLGRP_EN_NANDCLK_MASK 0x00000400
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#define CLKMGR_PERPLLGRP_EN_SDMMCCLK_MASK 0x00000100
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#define CLKMGR_PERPLLGRP_DIV_CAN0CLK_OFFSET 6
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#define CLKMGR_PERPLLGRP_DIV_CAN0CLK_MASK 0x000001c0
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#define CLKMGR_PERPLLGRP_DIV_CAN1CLK_OFFSET 9
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#define CLKMGR_PERPLLGRP_DIV_CAN1CLK_MASK 0x00000e00
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#define CLKMGR_PERPLLGRP_DIV_SPIMCLK_OFFSET 3
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#define CLKMGR_PERPLLGRP_DIV_SPIMCLK_OFFSET 3
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#define CLKMGR_PERPLLGRP_DIV_USBCLK_OFFSET 0
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#define CLKMGR_PERPLLGRP_DIV_USBCLK_MASK 0x00000007
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#define CLKMGR_PERPLLGRP_GPIODIV_GPIODBCLK_OFFSET 0
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#define CLKMGR_PERPLLGRP_GPIODIV_GPIODBCLK_MASK 0x00ffffff
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#define CLKMGR_PERPLLGRP_SRC_NAND_OFFSET 2
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#define CLKMGR_PERPLLGRP_SRC_NAND_MASK 0x0000000c
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#define CLKMGR_PERPLLGRP_SRC_QSPI_OFFSET 4
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#define CLKMGR_PERPLLGRP_SRC_QSPI_MASK 0x00000030
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#define CLKMGR_PERPLLGRP_SRC_RESET_VALUE 0x00000015
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#define CLKMGR_PERPLLGRP_SRC_SDMMC_OFFSET 0
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#define CLKMGR_PERPLLGRP_SRC_SDMMC_MASK 0x00000003
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#define CLKMGR_SDMMC_CLK_SRC_F2S 0x0
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#define CLKMGR_SDMMC_CLK_SRC_MAIN 0x1
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#define CLKMGR_SDMMC_CLK_SRC_PER 0x2
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#define CLKMGR_QSPI_CLK_SRC_F2S 0x0
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#define CLKMGR_QSPI_CLK_SRC_MAIN 0x1
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#define CLKMGR_QSPI_CLK_SRC_PER 0x2
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/* SDR PLL */
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#define CLKMGR_SDRPLLGRP_VCO_DENOM_OFFSET 16
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#define CLKMGR_SDRPLLGRP_VCO_DENOM_MASK 0x003f0000
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#define CLKMGR_SDRPLLGRP_VCO_NUMER_OFFSET 3
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#define CLKMGR_SDRPLLGRP_VCO_NUMER_MASK 0x0000fff8
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#define CLKMGR_SDRPLLGRP_VCO_OUTRESETALL BIT(24)
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#define CLKMGR_SDRPLLGRP_VCO_OUTRESETALL_OFFSET 24
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#define CLKMGR_SDRPLLGRP_VCO_OUTRESET_OFFSET 25
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#define CLKMGR_SDRPLLGRP_VCO_OUTRESET_MASK 0x7e000000
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#define CLKMGR_SDRPLLGRP_VCO_REGEXTSEL_MASK BIT(31)
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#define CLKMGR_SDRPLLGRP_VCO_RESET_VALUE 0x8001000d
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#define CLKMGR_SDRPLLGRP_VCO_SSRC_OFFSET 22
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#define CLKMGR_SDRPLLGRP_VCO_SSRC_MASK 0x00c00000
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#define CLKMGR_SDRPLLGRP_DDRDQSCLK_CNT_OFFSET 0
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#define CLKMGR_SDRPLLGRP_DDRDQSCLK_CNT_MASK 0x000001ff
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#define CLKMGR_SDRPLLGRP_DDRDQSCLK_PHASE_OFFSET 9
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#define CLKMGR_SDRPLLGRP_DDRDQSCLK_PHASE_MASK 0x00000e00
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#define CLKMGR_SDRPLLGRP_DDR2XDQSCLK_CNT_OFFSET 0
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#define CLKMGR_SDRPLLGRP_DDR2XDQSCLK_CNT_MASK 0x000001ff
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#define CLKMGR_SDRPLLGRP_DDR2XDQSCLK_PHASE_OFFSET 9
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#define CLKMGR_SDRPLLGRP_DDR2XDQSCLK_PHASE_MASK 0x00000e00
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#define CLKMGR_SDRPLLGRP_DDRDQCLK_CNT_OFFSET 0
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#define CLKMGR_SDRPLLGRP_DDRDQCLK_CNT_MASK 0x000001ff
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#define CLKMGR_SDRPLLGRP_DDRDQCLK_PHASE_OFFSET 9
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#define CLKMGR_SDRPLLGRP_DDRDQCLK_PHASE_MASK 0x00000e00
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#define CLKMGR_SDRPLLGRP_S2FUSER2CLK_CNT_OFFSET 0
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#define CLKMGR_SDRPLLGRP_S2FUSER2CLK_CNT_MASK 0x000001ff
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#define CLKMGR_SDRPLLGRP_S2FUSER2CLK_PHASE_OFFSET 9
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#define CLKMGR_SDRPLLGRP_S2FUSER2CLK_PHASE_MASK 0x00000e00
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#endif /* _CLOCK_MANAGER_GEN5_H_ */
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