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6b87abe3ac
SH4 and SH4A are compatible. But some instructions are different from these. In Linux kernel, It is treated as a separate CPU, but for now, I think that there is no need to divide especially in the U-Boot. This removes CONFIG_SH4A definition from source code, SH4A is treated as SH4. And this fix white space. Signed-off-by: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
86 lines
1.2 KiB
C
86 lines
1.2 KiB
C
/*
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* Copyright (C) 2007,2008 Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
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* Copyright (C) 2008 Renesas Solutions Corp.
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*
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* SPDX-License-Identifier: GPL-2.0+
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*/
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#include <common.h>
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#include <command.h>
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#include <asm/processor.h>
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#include <asm/io.h>
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#define STBCR4 0xFFFE040C
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#define cmt_clock_enable() do {\
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writeb(readb(STBCR4) & ~0x04, STBCR4);\
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} while (0)
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#define scif0_enable() do {\
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writeb(readb(STBCR4) & ~0x80, STBCR4);\
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} while (0)
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#define scif3_enable() do {\
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writeb(readb(STBCR4) & ~0x10, STBCR4);\
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} while (0)
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int checkcpu(void)
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{
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puts("CPU: SH2\n");
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return 0;
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}
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int cpu_init(void)
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{
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/* SCIF enable */
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#if defined(CONFIG_CONS_SCIF3)
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scif3_enable();
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#else
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scif0_enable();
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#endif
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/* CMT clock enable */
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cmt_clock_enable() ;
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return 0;
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}
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int cleanup_before_linux(void)
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{
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disable_interrupts();
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return 0;
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}
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int do_reset(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
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{
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disable_interrupts();
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reset_cpu(0);
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return 0;
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}
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void flush_cache(unsigned long addr, unsigned long size)
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{
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}
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void icache_enable(void)
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{
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}
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void icache_disable(void)
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{
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}
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int icache_status(void)
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{
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return 0;
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}
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void dcache_enable(void)
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{
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}
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void dcache_disable(void)
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{
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}
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int dcache_status(void)
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{
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return 0;
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}
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