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111fd19e3b
The multirate ethernet media access controller (mEMAC) interfaces to 10Gbps and below Ethernet/IEEE 802.3 networks via either RGMII/RMII interfaces or XAUI/XFI/SGMII/QSGMII using the high-speed SerDes interface. Signed-off-by: Sandeep Singh <Sandeep@freescale.com> Signed-off-by: Poonam Aggrwal <poonam.aggrwal@freescale.com> Signed-off-by: Roy Zang <tie-fei.zang@freescale.com> Signed-off-by: Andy Fleming <afleming@freescale.com>
151 lines
4.0 KiB
C
151 lines
4.0 KiB
C
/*
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* Copyright 2012 Freescale Semiconductor, Inc.
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* Andy Fleming <afleming@freescale.com>
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* Roy Zang <tie-fei.zang@freescale.com>
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License as
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* published by the Free Software Foundation; either version 2 of
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* the License, or (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
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* MA 02111-1307 USA
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* Some part is taken from tsec.c
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*/
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#include <common.h>
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#include <miiphy.h>
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#include <phy.h>
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#include <asm/io.h>
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#include <asm/fsl_memac.h>
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#include <fm_eth.h>
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/*
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* Write value to the PHY for this device to the register at regnum, waiting
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* until the write is done before it returns. All PHY configuration has to be
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* done through the TSEC1 MIIM regs
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*/
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int memac_mdio_write(struct mii_dev *bus, int port_addr, int dev_addr,
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int regnum, u16 value)
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{
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u32 mdio_ctl;
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struct memac_mdio_controller *regs = bus->priv;
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u32 c45 = 1; /* Default to 10G interface */
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if (dev_addr == MDIO_DEVAD_NONE) {
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c45 = 0; /* clause 22 */
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dev_addr = regnum & 0x1f;
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clrbits_be32(®s->mdio_stat, MDIO_STAT_ENC);
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} else {
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setbits_be32(®s->mdio_stat, MDIO_STAT_ENC);
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setbits_be32(®s->mdio_stat, MDIO_STAT_HOLD_15_CLK);
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}
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/* Wait till the bus is free */
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while ((in_be32(®s->mdio_stat)) & MDIO_STAT_BSY)
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;
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/* Set the port and dev addr */
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mdio_ctl = MDIO_CTL_PORT_ADDR(port_addr) | MDIO_CTL_DEV_ADDR(dev_addr);
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out_be32(®s->mdio_ctl, mdio_ctl);
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/* Set the register address */
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if (c45)
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out_be32(®s->mdio_addr, regnum & 0xffff);
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/* Wait till the bus is free */
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while ((in_be32(®s->mdio_stat)) & MDIO_STAT_BSY)
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;
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/* Write the value to the register */
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out_be32(®s->mdio_data, MDIO_DATA(value));
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/* Wait till the MDIO write is complete */
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while ((in_be32(®s->mdio_data)) & MDIO_DATA_BSY)
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;
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return 0;
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}
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/*
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* Reads from register regnum in the PHY for device dev, returning the value.
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* Clears miimcom first. All PHY configuration has to be done through the
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* TSEC1 MIIM regs
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*/
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int memac_mdio_read(struct mii_dev *bus, int port_addr, int dev_addr,
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int regnum)
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{
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u32 mdio_ctl;
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struct memac_mdio_controller *regs = bus->priv;
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u32 c45 = 1;
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if (dev_addr == MDIO_DEVAD_NONE) {
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c45 = 0; /* clause 22 */
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dev_addr = regnum & 0x1f;
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clrbits_be32(®s->mdio_stat, MDIO_STAT_ENC);
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} else {
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setbits_be32(®s->mdio_stat, MDIO_STAT_ENC);
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setbits_be32(®s->mdio_stat, MDIO_STAT_HOLD_15_CLK);
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}
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/* Wait till the bus is free */
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while ((in_be32(®s->mdio_stat)) & MDIO_STAT_BSY)
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;
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/* Set the Port and Device Addrs */
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mdio_ctl = MDIO_CTL_PORT_ADDR(port_addr) | MDIO_CTL_DEV_ADDR(dev_addr);
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out_be32(®s->mdio_ctl, mdio_ctl);
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/* Set the register address */
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if (c45)
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out_be32(®s->mdio_addr, regnum & 0xffff);
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/* Wait till the bus is free */
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while ((in_be32(®s->mdio_stat)) & MDIO_STAT_BSY)
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;
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/* Initiate the read */
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mdio_ctl |= MDIO_CTL_READ;
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out_be32(®s->mdio_ctl, mdio_ctl);
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/* Wait till the MDIO write is complete */
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while ((in_be32(®s->mdio_data)) & MDIO_DATA_BSY)
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;
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/* Return all Fs if nothing was there */
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if (in_be32(®s->mdio_stat) & MDIO_STAT_RD_ER)
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return 0xffff;
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return in_be32(®s->mdio_data) & 0xffff;
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}
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int memac_mdio_reset(struct mii_dev *bus)
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{
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return 0;
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}
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int fm_memac_mdio_init(bd_t *bis, struct memac_mdio_info *info)
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{
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struct mii_dev *bus = mdio_alloc();
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if (!bus) {
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printf("Failed to allocate FM TGEC MDIO bus\n");
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return -1;
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}
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bus->read = memac_mdio_read;
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bus->write = memac_mdio_write;
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bus->reset = memac_mdio_reset;
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sprintf(bus->name, info->name);
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bus->priv = info->regs;
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return mdio_register(bus);
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}
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