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	Signed-off-by: Wolfgang Denk <wd@denx.de> [trini: Fixup common/cmd_io.c] Signed-off-by: Tom Rini <trini@ti.com>
		
			
				
	
	
		
			115 lines
		
	
	
		
			2.7 KiB
		
	
	
	
		
			C
		
	
	
	
	
	
			
		
		
	
	
			115 lines
		
	
	
		
			2.7 KiB
		
	
	
	
		
			C
		
	
	
	
	
	
| /*
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|  * Copyright (C) 2008, Guennadi Liakhovetski <lg@denx.de>
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|  *
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|  * SPDX-License-Identifier:	GPL-2.0+
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|  */
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| 
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| #include <common.h>
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| #include <netdev.h>
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| #include <asm/io.h>
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| #include <asm/arch/clock.h>
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| #include <asm/arch/imx-regs.h>
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| #include <asm/arch/sys_proto.h>
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| 
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| DECLARE_GLOBAL_DATA_PTR;
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| 
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| int dram_init(void)
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| {
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| 	/* dram_init must store complete ramsize in gd->ram_size */
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| 	gd->ram_size = get_ram_size((void *)PHYS_SDRAM_1,
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| 				PHYS_SDRAM_1_SIZE);
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| 	return 0;
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| }
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| 
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| int board_early_init_f(void)
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| {
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| 	int i;
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| 
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| 	/* CS0: Nor Flash */
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| 	/*
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| 	 * CS0L and CS0A values are from the RedBoot sources by Freescale
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| 	 * and are also equal to those used by Sascha Hauer for the Phytec
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| 	 * i.MX31 board. CS0U is just a slightly optimized hardware default:
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| 	 * the only non-zero field "Wait State Control" is set to half the
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| 	 * default value.
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| 	 */
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| 	static const struct mxc_weimcs cs0 = {
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| 		/*    sp wp bcd bcs psz pme sync dol cnc wsc ew wws edc */
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| 		CSCR_U(0, 0,  0,  0,  0,  0,   0,  0,  0, 15, 0,  0,  0),
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| 		/*   oea oen ebwa ebwn csa ebc dsz csn psr cre wrap csen */
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| 		CSCR_L(1,  0,   0,   0,  0,  1,  5,  0,  0,  0,   1,   1),
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| 		/*  ebra ebrn rwa rwn mum lah lbn lba dww dct wwu age cnc2 fce*/
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| 		CSCR_A(0,   0,  7,  2,  0,  0,  2,  1,  0,  0,  0,  0,   0,   0)
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| 	};
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| 
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| 	mxc_setup_weimcs(0, &cs0);
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| 
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| 	/* setup pins for UART1 */
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| 	mx31_gpio_mux(MUX_RXD1__UART1_RXD_MUX);
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| 	mx31_gpio_mux(MUX_TXD1__UART1_TXD_MUX);
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| 	mx31_gpio_mux(MUX_RTS1__UART1_RTS_B);
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| 	mx31_gpio_mux(MUX_CTS1__UART1_CTS_B);
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| 
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| 	/* SPI2 */
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| 	mx31_gpio_mux(MUX_CSPI2_SS2__CSPI2_SS2_B);
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| 	mx31_gpio_mux(MUX_CSPI2_SCLK__CSPI2_CLK);
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| 	mx31_gpio_mux(MUX_CSPI2_SPI_RDY__CSPI2_DATAREADY_B);
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| 	mx31_gpio_mux(MUX_CSPI2_MOSI__CSPI2_MOSI);
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| 	mx31_gpio_mux(MUX_CSPI2_MISO__CSPI2_MISO);
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| 	mx31_gpio_mux(MUX_CSPI2_SS0__CSPI2_SS0_B);
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| 	mx31_gpio_mux(MUX_CSPI2_SS1__CSPI2_SS1_B);
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| 
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| 	/* start SPI2 clock */
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| 	__REG(CCM_CGR2) = __REG(CCM_CGR2) | (3 << 4);
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| 
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| 	/* PBC setup */
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| 	/* Enable UART transceivers also reset the Ethernet/external UART */
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| 	readw(CS4_BASE + 4);
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| 
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| 	writew(0x8023, CS4_BASE + 4);
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| 
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| 	/* RedBoot also has an empty loop with 100000 iterations here -
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| 	 * clock doesn't run yet */
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| 	for (i = 0; i < 100000; i++)
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| 		;
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| 
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| 	/* Clear the reset, toggle the LEDs */
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| 	writew(0xDF, CS4_BASE + 6);
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| 
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| 	/* clock still doesn't run */
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| 	for (i = 0; i < 100000; i++)
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| 		;
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| 
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| 	/* See 1.5.4 in IMX31ADSE_PERI_BUS_CNTRL_CPLD_RM.pdf */
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| 	readb(CS4_BASE + 8);
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| 	readb(CS4_BASE + 7);
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| 	readb(CS4_BASE + 8);
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| 	readb(CS4_BASE + 7);
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| 
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| 	return 0;
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| }
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| 
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| int board_init(void)
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| {
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| 	gd->bd->bi_boot_params = 0x80000100;	/* adress of boot parameters */
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| 
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| 	return 0;
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| }
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| 
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| int checkboard(void)
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| {
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| 	printf("Board: MX31ADS\n");
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| 	return 0;
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| }
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| 
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| #ifdef CONFIG_CMD_NET
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| int board_eth_init(bd_t *bis)
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| {
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| 	int rc = 0;
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| #ifdef CONFIG_CS8900
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| 	rc = cs8900_initialize(0, CONFIG_CS8900_BASE);
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| #endif
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| 	return rc;
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| }
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| #endif
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