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c978b52410
The Xtensa processor architecture is a configurable, extensible, and synthesizable 32-bit RISC processor core provided by Tensilica, inc. This is the second part of the basic architecture port, adding the 'arch/xtensa' directory and a readme file. Signed-off-by: Chris Zankel <chris@zankel.net> Signed-off-by: Max Filippov <jcmvbkbc@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: Tom Rini <trini@konsulko.com>
61 lines
1.1 KiB
C
61 lines
1.1 KiB
C
/*
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* (C) Copyright 2008 - 2013 Tensilica Inc.
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* (C) Copyright 2014 - 2016 Cadence Design Systems Inc.
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*
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* SPDX-License-Identifier: GPL-2.0+
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*/
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#include <common.h>
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#include <asm/cache.h>
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/*
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* We currently run always with caches enabled when running from memory.
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* Xtensa version D or later will support changing cache behavior, so
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* we could implement it if necessary.
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*/
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int dcache_status(void)
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{
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return 1;
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}
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void dcache_enable(void)
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{
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}
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void dcache_disable(void)
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{
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}
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void flush_cache(ulong start_addr, ulong size)
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{
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__flush_invalidate_dcache_range(start_addr, size);
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__invalidate_icache_range(start_addr, size);
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}
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void flush_dcache_all(void)
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{
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__flush_dcache_all();
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__invalidate_icache_all();
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}
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void flush_dcache_range(ulong start_addr, ulong end_addr)
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{
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__flush_invalidate_dcache_range(start_addr, end_addr - start_addr);
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}
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void invalidate_dcache_range(ulong start, ulong stop)
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{
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__invalidate_dcache_range(start, stop - start);
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}
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void invalidate_dcache_all(void)
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{
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__invalidate_dcache_all();
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}
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void invalidate_icache_all(void)
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{
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__invalidate_icache_all();
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}
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