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2b4ffbf6b4
This syncs drivers/ddr/marvell/a38x/ with the mv_ddr-armada-17.10 branch of https://github.com/MarvellEmbeddedProcessors/mv-ddr-marvell.git. The upstream code is incorporated omitting the ddr4 and apn806 and folding the nested a38x directory up one level. After that a semi-automated step is used to drop unused features with unifdef find drivers/ddr/marvell/a38x/ -name '*.[ch]' | \ xargs unifdef -m -UMV_DDR -UMV_DDR_ATF -UCONFIG_DDR4 \ -UCONFIG_APN806 -UCONFIG_MC_STATIC \ -UCONFIG_MC_STATIC_PRINT -UCONFIG_PHY_STATIC \ -UCONFIG_64BIT INTER_REGS_BASE is updated to be defined as SOC_REGS_PHY_BASE. Some now empty files are removed and the ternary license is replaced with a SPDX GPL-2.0+ identifier. Signed-off-by: Chris Packham <judge.packham@gmail.com> Signed-off-by: Stefan Roese <sr@denx.de>
95 lines
2.1 KiB
C
95 lines
2.1 KiB
C
/* SPDX-License-Identifier: GPL-2.0 */
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/*
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* Copyright (C) Marvell International Ltd. and its affiliates
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*/
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#ifndef _DDR3_TRAINING_IP_DB_H_
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#define _DDR3_TRAINING_IP_DB_H_
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enum hws_pattern {
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PATTERN_PBS1,
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PATTERN_PBS2,
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PATTERN_PBS3,
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PATTERN_TEST,
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PATTERN_RL,
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PATTERN_RL2,
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PATTERN_STATIC_PBS,
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PATTERN_KILLER_DQ0,
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PATTERN_KILLER_DQ1,
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PATTERN_KILLER_DQ2,
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PATTERN_KILLER_DQ3,
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PATTERN_KILLER_DQ4,
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PATTERN_KILLER_DQ5,
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PATTERN_KILLER_DQ6,
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PATTERN_KILLER_DQ7,
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PATTERN_VREF,
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PATTERN_FULL_SSO0,
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PATTERN_FULL_SSO1,
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PATTERN_FULL_SSO2,
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PATTERN_FULL_SSO3,
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PATTERN_LAST,
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PATTERN_SSO_FULL_XTALK_DQ0,
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PATTERN_SSO_FULL_XTALK_DQ1,
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PATTERN_SSO_FULL_XTALK_DQ2,
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PATTERN_SSO_FULL_XTALK_DQ3,
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PATTERN_SSO_FULL_XTALK_DQ4,
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PATTERN_SSO_FULL_XTALK_DQ5,
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PATTERN_SSO_FULL_XTALK_DQ6,
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PATTERN_SSO_FULL_XTALK_DQ7,
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PATTERN_SSO_XTALK_FREE_DQ0,
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PATTERN_SSO_XTALK_FREE_DQ1,
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PATTERN_SSO_XTALK_FREE_DQ2,
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PATTERN_SSO_XTALK_FREE_DQ3,
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PATTERN_SSO_XTALK_FREE_DQ4,
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PATTERN_SSO_XTALK_FREE_DQ5,
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PATTERN_SSO_XTALK_FREE_DQ6,
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PATTERN_SSO_XTALK_FREE_DQ7,
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PATTERN_ISI_XTALK_FREE
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};
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enum mv_wl_supp_mode {
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WRITE_LEVELING_SUPP_REG_MODE,
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WRITE_LEVELING_SUPP_ECC_MODE_DATA_PUPS,
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WRITE_LEVELING_SUPP_ECC_MODE_ECC_PUP4,
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WRITE_LEVELING_SUPP_ECC_MODE_ECC_PUP3,
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WRITE_LEVELING_SUPP_ECC_MODE_ECC_PUP8
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};
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enum mv_ddr_dev_attribute {
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MV_ATTR_TIP_REV,
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MV_ATTR_PHY_EDGE,
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MV_ATTR_OCTET_PER_INTERFACE,
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MV_ATTR_PLL_BEFORE_INIT,
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MV_ATTR_TUNE_MASK,
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MV_ATTR_INIT_FREQ,
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MV_ATTR_MID_FREQ,
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MV_ATTR_DFS_LOW_FREQ,
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MV_ATTR_DFS_LOW_PHY,
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MV_ATTR_DELAY_ENABLE,
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MV_ATTR_CK_DELAY,
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MV_ATTR_CA_DELAY,
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MV_ATTR_INTERLEAVE_WA,
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MV_ATTR_LAST
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};
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enum mv_ddr_tip_revison {
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MV_TIP_REV_NA,
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MV_TIP_REV_1, /* NP5 */
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MV_TIP_REV_2, /* BC2 */
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MV_TIP_REV_3, /* AC3 */
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MV_TIP_REV_4, /* A-380/A-390 */
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MV_TIP_REV_LAST
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};
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enum mv_ddr_phy_edge {
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MV_DDR_PHY_EDGE_POSITIVE,
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MV_DDR_PHY_EDGE_NEGATIVE
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};
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/* Device attribute functions */
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void ddr3_tip_dev_attr_init(u32 dev_num);
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u32 ddr3_tip_dev_attr_get(u32 dev_num, enum mv_ddr_dev_attribute attr_id);
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void ddr3_tip_dev_attr_set(u32 dev_num, enum mv_ddr_dev_attribute attr_id, u32 value);
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#endif /* _DDR3_TRAINING_IP_DB_H_ */
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