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This patch provides the code to calibrate the DDR's DQS to DQ signals (RDLVL). It is based on: VFxxx Controller Reference Manual, Rev. 0, 10/2016, page 1600 10.1.6.16.4.1 "Software Read Leveling in MC Evaluation Mode" and NXP's community thread: "Vybrid: About DDR leveling feature on DDRMC." https://community.nxp.com/thread/395323 Signed-off-by: Lukasz Majewski <lukma@denx.de>
46 lines
1013 B
C
46 lines
1013 B
C
/* SPDX-License-Identifier: GPL-2.0+ */
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/*
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* ddrmc DDR3 calibration code for NXP's VF610
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*
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* Copyright (C) 2018 DENX Software Engineering
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* Lukasz Majewski, DENX Software Engineering, lukma@denx.de
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*
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*/
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#ifndef __DDRMC_VF610_CALIBRATOIN_H_
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#define __DDRMC_VF610_CALIBRATOIN_H_
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/*
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* Number of "samples" in the calibration bitmap
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* to be considered during calibration.
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*/
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#define N_SAMPLES 3
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/*
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* Constants to indicate if we are looking for a rising or
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* falling edge in the calibration bitmap
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*/
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enum edge {
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FALLING_EDGE = 1,
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RISING_EDGE
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};
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/*
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* The max number of delay elements when DQS to DQ setting
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*/
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#define DDRMC_DQS_DQ_MAX_DELAY 0xFF
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/**
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* ddrmc_calibration - Vybrid's (VF610) DDR3 calibration code
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*
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* This function is calculating proper memory controller values
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* during run time.
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*
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* @param ddrmr_regs - memory controller registers
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*
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* @return 0 on success, otherwise error code
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*/
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int ddrmc_calibration(struct ddrmr_regs *ddrmr);
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#endif /* __DDRMC_VF610_CALIBRATOIN_H_ */
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