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7c75f7f1b2
In preparation to add support for the Dragonboard820c (APQ8096), refactor the current Snapdragon clock driver. No new functionality has been added. Signed-off-by: Jorge Ramirez-Ortiz <jorge.ramirez-ortiz@linaro.org>
41 lines
845 B
C
41 lines
845 B
C
/*
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* Qualcomm APQ8016, APQ8096
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*
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* (C) Copyright 2017 Jorge Ramirez-Ortiz <jorge.ramirez-ortiz@linaro.org>
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*
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* SPDX-License-Identifier: GPL-2.0+
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*/
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#ifndef _CLOCK_SNAPDRAGON_H
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#define _CLOCK_SNAPDRAGON_H
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#define CFG_CLK_SRC_CXO (0 << 8)
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#define CFG_CLK_SRC_GPLL0 (1 << 8)
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#define CFG_CLK_SRC_MASK (7 << 8)
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struct gpll0_ctrl {
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uintptr_t status;
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int status_bit;
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uintptr_t ena_vote;
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int vote_bit;
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};
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struct bcr_regs {
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uintptr_t cfg_rcgr;
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uintptr_t cmd_rcgr;
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uintptr_t M;
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uintptr_t N;
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uintptr_t D;
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};
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struct msm_clk_priv {
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phys_addr_t base;
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};
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void clk_enable_gpll0(phys_addr_t base, const struct gpll0_ctrl *pll0);
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void clk_bcr_update(phys_addr_t apps_cmd_rgcr);
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void clk_enable_cbc(phys_addr_t cbcr);
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void clk_rcg_set_rate_mnd(phys_addr_t base, const struct bcr_regs *regs,
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int div, int m, int n, int source);
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#endif
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