mirror of
https://xff.cz/git/u-boot/
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7f8a6a66af
Add devicetree support for iMXQXP AI_ML board from Einfochips. Signed-off-by: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org> Reviewed-by: Peng Fan <peng.fan@nxp.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
182 lines
4.2 KiB
Plaintext
182 lines
4.2 KiB
Plaintext
// SPDX-License-Identifier: GPL-2.0+
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/*
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* Copyright 2018 Einfochips
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* Copyright 2019 Linaro Ltd.
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*/
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/dts-v1/;
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#include "fsl-imx8qxp.dtsi"
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#include "fsl-imx8qxp-ai_ml-u-boot.dtsi"
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/ {
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model = "Einfochips i.MX8QXP AI_ML";
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compatible = "einfochips,imx8qxp-ai_ml", "fsl,imx8qxp";
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chosen {
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bootargs = "console=ttyLP2,115200 earlycon=lpuart32,0x5a080000,115200";
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stdout-path = &lpuart2;
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};
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memory@80000000 {
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device_type = "memory";
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reg = <0x00000000 0x80000000 0 0x80000000>;
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};
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};
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&lpuart0 {
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pinctrl-names = "default";
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pinctrl-0 = <&pinctrl_lpuart0>;
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status = "okay";
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};
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&lpuart1 {
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pinctrl-names = "default";
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pinctrl-0 = <&pinctrl_lpuart1>;
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status = "okay";
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};
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&lpuart2 {
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pinctrl-names = "default";
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pinctrl-0 = <&pinctrl_lpuart2>;
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status = "okay";
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};
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&lpuart3 {
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pinctrl-names = "default";
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pinctrl-0 = <&pinctrl_lpuart3>;
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status = "okay";
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};
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&fec1 {
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pinctrl-names = "default";
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pinctrl-0 = <&pinctrl_fec1>;
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phy-mode = "rgmii";
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phy-handle = <ðphy0>;
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fsl,ar8031-phy-fixup;
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fsl,magic-packet;
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phy-reset-gpios = <&gpio4 14 GPIO_ACTIVE_LOW>;
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phy-reset-duration = <10>;
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phy-reset-post-delay = <150>;
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status = "okay";
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mdio {
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#address-cells = <1>;
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#size-cells = <0>;
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ethphy0: ethernet-phy@0 {
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compatible = "ethernet-phy-ieee802.3-c22";
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reg = <0>;
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};
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};
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};
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/* LS-I2C1 */
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&i2c1 {
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#address-cells = <1>;
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#size-cells = <0>;
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clock-frequency = <100000>;
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pinctrl-names = "default";
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pinctrl-0 = <&pinctrl_lpi2c1>;
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status = "okay";
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};
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&usdhc1 {
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pinctrl-names = "default";
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pinctrl-0 = <&pinctrl_usdhc1>;
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bus-width = <4>;
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no-sd;
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#address-cells = <1>;
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#size-cells = <0>;
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status = "okay";
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};
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&usdhc2 {
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pinctrl-names = "default";
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pinctrl-0 = <&pinctrl_usdhc2>;
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bus-width = <4>;
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cd-gpios = <&gpio4 22 GPIO_ACTIVE_LOW>;
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status = "okay";
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};
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&iomuxc {
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pinctrl_fec1: fec1grp {
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fsl,pins = <
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SC_P_COMP_CTL_GPIO_1V8_3V3_ENET_ENETB0_PAD 0x000014a0
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SC_P_COMP_CTL_GPIO_1V8_3V3_ENET_ENETB1_PAD 0x000014a0
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SC_P_ENET0_MDC_CONN_ENET0_MDC 0x06000020
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SC_P_ENET0_MDIO_CONN_ENET0_MDIO 0x06000020
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SC_P_ENET0_RGMII_TX_CTL_CONN_ENET0_RGMII_TX_CTL 0x06000020
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SC_P_ENET0_RGMII_TXC_CONN_ENET0_RGMII_TXC 0x06000020
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SC_P_ENET0_RGMII_TXD0_CONN_ENET0_RGMII_TXD0 0x06000020
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SC_P_ENET0_RGMII_TXD1_CONN_ENET0_RGMII_TXD1 0x06000020
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SC_P_ENET0_RGMII_TXD2_CONN_ENET0_RGMII_TXD2 0x06000020
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SC_P_ENET0_RGMII_TXD3_CONN_ENET0_RGMII_TXD3 0x06000020
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SC_P_ENET0_RGMII_RXC_CONN_ENET0_RGMII_RXC 0x06000020
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SC_P_ENET0_RGMII_RX_CTL_CONN_ENET0_RGMII_RX_CTL 0x06000020
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SC_P_ENET0_RGMII_RXD0_CONN_ENET0_RGMII_RXD0 0x06000020
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SC_P_ENET0_RGMII_RXD1_CONN_ENET0_RGMII_RXD1 0x06000020
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SC_P_ENET0_RGMII_RXD2_CONN_ENET0_RGMII_RXD2 0x06000020
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SC_P_ENET0_RGMII_RXD3_CONN_ENET0_RGMII_RXD3 0x06000020
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>;
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};
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pinctrl_lpi2c1: lpi2c1grp {
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fsl,pins = <
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SC_P_USB_SS3_TC1_ADMA_I2C1_SCL 0x06000021
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SC_P_USB_SS3_TC3_ADMA_I2C1_SDA 0x06000021
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>;
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};
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pinctrl_lpuart0: lpuart0grp {
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fsl,pins = <
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SC_P_UART0_RX_ADMA_UART0_RX 0X06000020
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SC_P_UART0_TX_ADMA_UART0_TX 0X06000020
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>;
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};
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pinctrl_lpuart1: lpuart1grp {
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fsl,pins = <
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SC_P_UART1_RX_ADMA_UART1_RX 0X06000020
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SC_P_UART1_TX_ADMA_UART1_TX 0X06000020
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>;
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};
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pinctrl_lpuart2: lpuart2grp {
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fsl,pins = <
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SC_P_UART2_RX_ADMA_UART2_RX 0X06000020
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SC_P_UART2_TX_ADMA_UART2_TX 0X06000020
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>;
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};
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pinctrl_lpuart3: lpuart3grp {
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fsl,pins = <
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SC_P_FLEXCAN2_RX_ADMA_UART3_RX 0X06000020
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SC_P_FLEXCAN2_TX_ADMA_UART3_TX 0X06000020
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>;
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};
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pinctrl_usdhc1: usdhc1grp {
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fsl,pins = <
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SC_P_EMMC0_CLK_CONN_EMMC0_CLK 0x06000041
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SC_P_EMMC0_CMD_CONN_EMMC0_CMD 0x00000021
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SC_P_EMMC0_DATA0_CONN_EMMC0_DATA0 0x00000021
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SC_P_EMMC0_DATA1_CONN_EMMC0_DATA1 0x00000021
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SC_P_EMMC0_DATA2_CONN_EMMC0_DATA2 0x00000021
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SC_P_EMMC0_DATA3_CONN_EMMC0_DATA3 0x00000021
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>;
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};
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pinctrl_usdhc2: usdhc2grp {
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fsl,pins = <
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SC_P_USDHC1_CLK_CONN_USDHC1_CLK 0x06000041
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SC_P_USDHC1_CMD_CONN_USDHC1_CMD 0x00000021
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SC_P_USDHC1_DATA0_CONN_USDHC1_DATA0 0x00000021
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SC_P_USDHC1_DATA1_CONN_USDHC1_DATA1 0x00000021
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SC_P_USDHC1_DATA2_CONN_USDHC1_DATA2 0x00000021
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SC_P_USDHC1_DATA3_CONN_USDHC1_DATA3 0x00000021
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SC_P_USDHC1_VSELECT_CONN_USDHC1_VSELECT 0x00000021
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>;
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};
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};
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