Tien Fong Chee c1cf539180 ARM: socfpga: Moving the watchdog reset to the for-loop status polling ...

Current watchdog reset is misplaced after for-loop status polling, so
this poses a risk that watchdog can't be reset timely if polling taking
longer than watchdog timeout. This patch moving the watchdog reset
into polling to ensure the watchdog can be reset timely.

Signed-off-by: Tien Fong Chee <tien.fong.chee@intel.com>

2019-05-10 22:48:10 +02:00

..

ACEX1K.c

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altera.c

arm: socfpga: stratix10: Add Stratix10 FPGA into FPGA device table

2018-12-20 17:12:25 +01:00

cyclon2.c

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2018-05-07 09:34:12 -04:00

fpga.c

cmd: fpga: Add support to load secure bitstreams

2018-06-01 11:37:31 +02:00

ivm_core.c

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2018-05-07 09:34:12 -04:00

Kconfig

arm: socfpga: stratix10: Add Stratix 10 FPGA Reconfiguration Driver

2018-12-20 17:12:25 +01:00

lattice.c

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Makefile

arm: socfpga: stratix10: Add Stratix 10 FPGA Reconfiguration Driver

2018-12-20 17:12:25 +01:00

socfpga_arria10.c

ARM: socfpga: Moving the watchdog reset to the for-loop status polling

2019-05-10 22:48:10 +02:00

socfpga_gen5.c

arm: socfpga: fpga: fix type of local variable

2018-10-31 01:41:10 +01:00

socfpga.c

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2018-05-07 09:34:12 -04:00

spartan2.c

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2018-05-07 09:34:12 -04:00

spartan3.c

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2018-05-07 09:34:12 -04:00

stratix10.c

ARM: socfpga: stratix10: Return valid error code from FPGA driver

2019-02-18 13:00:54 +01:00

stratixII.c

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2018-05-07 09:34:12 -04:00

stratixv.c

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2018-05-07 09:34:12 -04:00

virtex2.c

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2018-05-07 09:34:12 -04:00

xilinx.c

fpga: zynqmp: Add secure bitstream loading for ZynqMP

2018-06-01 11:37:31 +02:00

zynqmppl.c

fpga: zynqmp: show an error message when FPGA programming fails

2019-01-24 10:03:43 +01:00

zynqpl.c

arm: zynq: Add an info message about post config

2019-04-16 11:51:34 +02:00