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u-boot-megous/arch/riscv/dts
Torsten Duwe 6164d86984 riscv: jh7110: enable riscv,timer in the device tree
The JH7110 has the arhitectural CPU timer on all 5 rv64 cores.
Note that in the device tree.

Signed-off-by: Torsten Duwe <duwe@suse.de>
Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com>
2023-09-05 10:53:36 +08:00
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