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f3bb63a304
MX25 has a different version of the fsl_nfc flash controller known as version 1.1. Add support to the nand_spl fsl_nfc driver Versioning differs from mainline mxc kernel driver no consensus yet on if the naming here and in Redboot or the kernel is "correct". Signed-off-by: John Rigby <jcrigby@gmail.com> Signed-off-by: Wolfgang Denk <wd@denx.de> CC: Scott Wood <scottwood@freescale.com>
172 lines
4.3 KiB
C
172 lines
4.3 KiB
C
/*
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* (c) 2009 Magnus Lilja <lilja.magnus@gmail.com>
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*
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* See file CREDITS for list of people who contributed to this
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* project.
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License as
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* published by the Free Software Foundation; either version 2 of
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* the License, or (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
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* MA 02111-1307 USA
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*/
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#ifndef __FSL_NFC_H
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#define __FSL_NFC_H
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/*
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* TODO: Use same register defs for nand_spl mxc nand driver
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* and mtd mxc nand driver.
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*
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* Register map and bit definitions for the Freescale NAND Flash
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* Controller present in various i.MX devices.
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*
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* MX31 and MX27 have version 1 which has
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* 4 512 byte main buffers and
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* 4 16 byte spare buffers
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* to support up to 2K byte pagesize nand.
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* Reading or writing a 2K page requires 4 FDI/FDO cycles.
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*
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* MX25 has version 1.1 which has
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* 8 512 byte main buffers and
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* 8 64 byte spare buffers
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* to support up to 4K byte pagesize nand.
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* Reading or writing a 2K or 4K page requires only 1 FDI/FDO cycle.
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* Also some of registers are moved and/or changed meaning as seen below.
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*/
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#if defined(CONFIG_MX31) || defined(CONFIG_MX27)
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#define MXC_NFC_V1
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#elif defined(CONFIG_MX25)
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#define MXC_NFC_V1_1
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#else
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#warning "MXC NFC version not defined"
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#endif
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#if defined(MXC_NFC_V1)
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#define NAND_MXC_NR_BUFS 4
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#define NAND_MXC_SPARE_BUF_SIZE 16
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#define NAND_MXC_REG_OFFSET 0xe00
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#define NAND_MXC_2K_MULTI_CYCLE 1
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#elif defined(MXC_NFC_V1_1)
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#define NAND_MXC_NR_BUFS 8
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#define NAND_MXC_SPARE_BUF_SIZE 64
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#define NAND_MXC_REG_OFFSET 0x1e00
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#else
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#error "define CONFIG_NAND_MXC_VXXX to use the mxc spl_nand driver"
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#endif
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struct fsl_nfc_regs {
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u32 main_area[NAND_MXC_NR_BUFS][512/4];
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u32 spare_area[NAND_MXC_NR_BUFS][NAND_MXC_SPARE_BUF_SIZE/4];
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/*
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* reserved size is offset of nfc registers
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* minus total main and spare sizes
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*/
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u8 reserved1[NAND_MXC_REG_OFFSET
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- NAND_MXC_NR_BUFS * (512 + NAND_MXC_SPARE_BUF_SIZE)];
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#if defined(MXC_NFC_V1)
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u16 bufsiz;
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u16 reserved2;
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u16 buffer_address;
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u16 flash_add;
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u16 flash_cmd;
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u16 configuration;
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u16 ecc_status_result;
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u16 ecc_rslt_main_area;
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u16 ecc_rslt_spare_area;
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u16 nf_wr_prot;
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u16 unlock_start_blk_add;
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u16 unlock_end_blk_add;
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u16 nand_flash_wr_pr_st;
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u16 nand_flash_config1;
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u16 nand_flash_config2;
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#elif defined(MXC_NFC_V1_1)
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u16 reserved2[2];
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u16 buffer_address;
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u16 flash_add;
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u16 flash_cmd;
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u16 configuration;
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u16 ecc_status_result;
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u16 ecc_status_result2;
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u16 spare_area_size;
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u16 nf_wr_prot;
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u16 reserved3[2];
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u16 nand_flash_wr_pr_st;
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u16 nand_flash_config1;
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u16 nand_flash_config2;
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u16 reserved4;
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u16 unlock_start_blk_add0;
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u16 unlock_end_blk_add0;
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u16 unlock_start_blk_add1;
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u16 unlock_end_blk_add1;
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u16 unlock_start_blk_add2;
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u16 unlock_end_blk_add2;
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u16 unlock_start_blk_add3;
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u16 unlock_end_blk_add3;
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#endif
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};
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/*
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* Set INT to 0, FCMD to 1, rest to 0 in NFC_CONFIG2 Register for Command
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* operation
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*/
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#define NFC_CMD 0x1
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/*
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* Set INT to 0, FADD to 1, rest to 0 in NFC_CONFIG2 Register for Address
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* operation
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*/
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#define NFC_ADDR 0x2
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/*
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* Set INT to 0, FDI to 1, rest to 0 in NFC_CONFIG2 Register for Input
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* operation
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*/
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#define NFC_INPUT 0x4
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/*
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* Set INT to 0, FDO to 001, rest to 0 in NFC_CONFIG2 Register for Data
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* Output operation
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*/
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#define NFC_OUTPUT 0x8
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/*
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* Set INT to 0, FD0 to 010, rest to 0 in NFC_CONFIG2 Register for Read ID
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* operation
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*/
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#define NFC_ID 0x10
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/*
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* Set INT to 0, FDO to 100, rest to 0 in NFC_CONFIG2 Register for Read
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* Status operation
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*/
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#define NFC_STATUS 0x20
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/*
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* Set INT to 1, rest to 0 in NFC_CONFIG2 Register for Read Status
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* operation
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*/
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#define NFC_INT 0x8000
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#ifdef MXC_NFC_V1_1
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#define NFC_4_8N_ECC (1 << 0)
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#endif
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#define NFC_SP_EN (1 << 2)
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#define NFC_ECC_EN (1 << 3)
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#define NFC_INT_MSK (1 << 4)
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#define NFC_BIG (1 << 5)
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#define NFC_RST (1 << 6)
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#define NFC_CE (1 << 7)
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#define NFC_ONE_CYCLE (1 << 8)
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#endif /* __FSL_NFC_H */
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