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aaa449fb27
AM654 has an arasan sdhci controller and a mmc phy attached to it. Add basic support for K3 specific arasan sdhci controller. Cc: Jaehoon Chung <jh80.chung@samsung.com> Reviewed-by: Tom Rini <trini@konsulko.com> Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
110 lines
2.5 KiB
C
110 lines
2.5 KiB
C
// SPDX-License-Identifier: GPL-2.0+
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/*
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* Copyright (C) 2018 Texas Instruments Incorporated - http://www.ti.com/
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*
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* Texas Instruments' K3 SD Host Controller Interface
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*/
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#include <clk.h>
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#include <common.h>
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#include <dm.h>
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#include <malloc.h>
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#include <power-domain.h>
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#include <sdhci.h>
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#define K3_ARASAN_SDHCI_MIN_FREQ 0
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struct k3_arasan_sdhci_plat {
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struct mmc_config cfg;
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struct mmc mmc;
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unsigned int f_max;
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};
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static int k3_arasan_sdhci_probe(struct udevice *dev)
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{
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struct k3_arasan_sdhci_plat *plat = dev_get_platdata(dev);
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struct mmc_uclass_priv *upriv = dev_get_uclass_priv(dev);
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struct sdhci_host *host = dev_get_priv(dev);
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struct power_domain sdhci_pwrdmn;
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struct clk clk;
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unsigned long clock;
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int ret;
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ret = power_domain_get_by_index(dev, &sdhci_pwrdmn, 0);
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if (ret) {
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dev_err(dev, "failed to get power domain\n");
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return ret;
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}
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ret = power_domain_on(&sdhci_pwrdmn);
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if (ret) {
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dev_err(dev, "Power domain on failed\n");
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return ret;
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}
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ret = clk_get_by_index(dev, 0, &clk);
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if (ret) {
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dev_err(dev, "failed to get clock\n");
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return ret;
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}
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clock = clk_get_rate(&clk);
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if (IS_ERR_VALUE(clock)) {
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dev_err(dev, "failed to get rate\n");
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return clock;
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}
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host->quirks = SDHCI_QUIRK_WAIT_SEND_CMD |
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SDHCI_QUIRK_BROKEN_R1B;
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host->max_clk = clock;
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ret = sdhci_setup_cfg(&plat->cfg, host, plat->f_max,
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K3_ARASAN_SDHCI_MIN_FREQ);
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host->mmc = &plat->mmc;
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if (ret)
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return ret;
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host->mmc->priv = host;
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host->mmc->dev = dev;
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upriv->mmc = host->mmc;
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return sdhci_probe(dev);
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}
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static int k3_arasan_sdhci_ofdata_to_platdata(struct udevice *dev)
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{
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struct k3_arasan_sdhci_plat *plat = dev_get_platdata(dev);
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struct sdhci_host *host = dev_get_priv(dev);
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host->name = dev->name;
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host->ioaddr = (void *)dev_read_addr(dev);
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host->bus_width = dev_read_u32_default(dev, "bus-width", 4);
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plat->f_max = dev_read_u32_default(dev, "max-frequency", 0);
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return 0;
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}
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static int k3_arasan_sdhci_bind(struct udevice *dev)
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{
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struct k3_arasan_sdhci_plat *plat = dev_get_platdata(dev);
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return sdhci_bind(dev, &plat->mmc, &plat->cfg);
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}
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static const struct udevice_id k3_arasan_sdhci_ids[] = {
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{ .compatible = "arasan,sdhci-5.1" },
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{ }
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};
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U_BOOT_DRIVER(k3_arasan_sdhci_drv) = {
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.name = "k3_arasan_sdhci",
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.id = UCLASS_MMC,
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.of_match = k3_arasan_sdhci_ids,
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.ofdata_to_platdata = k3_arasan_sdhci_ofdata_to_platdata,
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.ops = &sdhci_ops,
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.bind = k3_arasan_sdhci_bind,
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.probe = k3_arasan_sdhci_probe,
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.priv_auto_alloc_size = sizeof(struct sdhci_host),
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.platdata_auto_alloc_size = sizeof(struct k3_arasan_sdhci_plat),
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};
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