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https://xff.cz/git/u-boot/
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c9309f40a6
This function is a no-op. Remove it. Signed-off-by: Sean Anderson <seanga2@gmail.com> Link: https://lore.kernel.org/r/20231216193843.2463779-3-seanga2@gmail.com
612 lines
16 KiB
C
612 lines
16 KiB
C
// SPDX-License-Identifier: GPL-2.0+
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/*
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* (C) Copyright 2022-2023 Sumit Garg <sumit.garg@linaro.org>
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*
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* Qcom DWMAC specific glue layer
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*/
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#include <common.h>
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#include <asm/global_data.h>
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#include <asm/gpio.h>
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#include <asm/io.h>
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#include <clk.h>
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#include <dm.h>
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#include <dm/device_compat.h>
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#include <phy.h>
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#include <reset.h>
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#include <syscon.h>
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#include <linux/bitops.h>
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#include <linux/delay.h>
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#include "dwc_eth_qos.h"
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/* RGMII_IO_MACRO_CONFIG fields */
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#define RGMII_CONFIG_FUNC_CLK_EN BIT(30)
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#define RGMII_CONFIG_POS_NEG_DATA_SEL BIT(23)
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#define RGMII_CONFIG_GPIO_CFG_RX_INT GENMASK(21, 20)
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#define RGMII_CONFIG_GPIO_CFG_TX_INT GENMASK(19, 17)
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#define RGMII_CONFIG_MAX_SPD_PRG_9 GENMASK(16, 8)
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#define RGMII_CONFIG_MAX_SPD_PRG_2 GENMASK(7, 6)
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#define RGMII_CONFIG_INTF_SEL GENMASK(5, 4)
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#define RGMII_CONFIG_BYPASS_TX_ID_EN BIT(3)
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#define RGMII_CONFIG_LOOPBACK_EN BIT(2)
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#define RGMII_CONFIG_PROG_SWAP BIT(1)
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#define RGMII_CONFIG_DDR_MODE BIT(0)
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/* SDCC_HC_REG_DLL_CONFIG fields */
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#define SDCC_DLL_CONFIG_DLL_RST BIT(30)
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#define SDCC_DLL_CONFIG_PDN BIT(29)
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#define SDCC_DLL_CONFIG_MCLK_FREQ GENMASK(26, 24)
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#define SDCC_DLL_CONFIG_CDR_SELEXT GENMASK(23, 20)
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#define SDCC_DLL_CONFIG_CDR_EXT_EN BIT(19)
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#define SDCC_DLL_CONFIG_CK_OUT_EN BIT(18)
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#define SDCC_DLL_CONFIG_CDR_EN BIT(17)
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#define SDCC_DLL_CONFIG_DLL_EN BIT(16)
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#define SDCC_DLL_MCLK_GATING_EN BIT(5)
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#define SDCC_DLL_CDR_FINE_PHASE GENMASK(3, 2)
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/* SDCC_HC_REG_DDR_CONFIG fields */
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#define SDCC_DDR_CONFIG_PRG_DLY_EN BIT(31)
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#define SDCC_DDR_CONFIG_EXT_PRG_RCLK_DLY GENMASK(26, 21)
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#define SDCC_DDR_CONFIG_EXT_PRG_RCLK_DLY_CODE GENMASK(29, 27)
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#define SDCC_DDR_CONFIG_EXT_PRG_RCLK_DLY_EN BIT(30)
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#define SDCC_DDR_CONFIG_PRG_RCLK_DLY GENMASK(8, 0)
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/* SDCC_HC_REG_DLL_CONFIG2 fields */
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#define SDCC_DLL_CONFIG2_DLL_CLOCK_DIS BIT(21)
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#define SDCC_DLL_CONFIG2_MCLK_FREQ_CALC GENMASK(17, 10)
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#define SDCC_DLL_CONFIG2_DDR_TRAFFIC_INIT_SEL GENMASK(3, 2)
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#define SDCC_DLL_CONFIG2_DDR_TRAFFIC_INIT_SW BIT(1)
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#define SDCC_DLL_CONFIG2_DDR_CAL_EN BIT(0)
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/* SDC4_STATUS bits */
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#define SDC4_STATUS_DLL_LOCK BIT(7)
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/* RGMII_IO_MACRO_CONFIG2 fields */
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#define RGMII_CONFIG2_RSVD_CONFIG15 GENMASK(31, 17)
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#define RGMII_CONFIG2_RGMII_CLK_SEL_CFG BIT(16)
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#define RGMII_CONFIG2_TX_TO_RX_LOOPBACK_EN BIT(13)
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#define RGMII_CONFIG2_CLK_DIVIDE_SEL BIT(12)
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#define RGMII_CONFIG2_RX_PROG_SWAP BIT(7)
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#define RGMII_CONFIG2_DATA_DIVIDE_CLK_SEL BIT(6)
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#define RGMII_CONFIG2_TX_CLK_PHASE_SHIFT_EN BIT(5)
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struct dwmac_rgmii_regs {
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u32 io_macro_config; /* 0x00 */
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u32 sdcc_hc_dll_config; /* 0x04 */
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u32 reserved_1; /* 0x08 */
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u32 sdcc_hc_ddr_config; /* 0x0c */
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u32 sdcc_hc_dll_config2; /* 0x10 */
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u32 sdc4_status; /* 0x14 */
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u32 sdcc_usr_ctl; /* 0x18 */
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u32 io_macro_config2; /* 0x1c */
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u32 io_macro_debug1; /* 0x20 */
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u32 reserved_2; /* 0x24 */
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u32 emac_sys_low_power_dbg; /* 0x28 */
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u32 reserved_3[53]; /* upto 0x100 */
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};
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static struct dwmac_rgmii_regs emac_v2_3_0_por = {
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.io_macro_config = 0x00C01343,
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.sdcc_hc_dll_config = 0x2004642C,
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.sdcc_hc_ddr_config = 0x00000000,
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.sdcc_hc_dll_config2 = 0x00200000,
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.sdcc_usr_ctl = 0x00010800,
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.io_macro_config2 = 0x00002060
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};
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static void ethqos_set_func_clk_en(struct dwmac_rgmii_regs *regs)
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{
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setbits_le32(®s->io_macro_config, RGMII_CONFIG_FUNC_CLK_EN);
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}
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static int ethqos_dll_configure(struct udevice *dev,
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struct dwmac_rgmii_regs *regs)
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{
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unsigned int val;
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int retry = 1000;
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/* Set CDR_EN */
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setbits_le32(®s->sdcc_hc_dll_config, SDCC_DLL_CONFIG_CDR_EN);
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/* Set CDR_EXT_EN */
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setbits_le32(®s->sdcc_hc_dll_config, SDCC_DLL_CONFIG_CDR_EXT_EN);
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/* Clear CK_OUT_EN */
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clrbits_le32(®s->sdcc_hc_dll_config, SDCC_DLL_CONFIG_CK_OUT_EN);
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/* Set DLL_EN */
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setbits_le32(®s->sdcc_hc_dll_config, SDCC_DLL_CONFIG_DLL_EN);
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clrbits_le32(®s->sdcc_hc_dll_config, SDCC_DLL_MCLK_GATING_EN);
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clrbits_le32(®s->sdcc_hc_dll_config, SDCC_DLL_CDR_FINE_PHASE);
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/* Wait for CK_OUT_EN clear */
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do {
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val = readl(®s->sdcc_hc_dll_config);
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val &= SDCC_DLL_CONFIG_CK_OUT_EN;
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if (!val)
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break;
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mdelay(1);
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retry--;
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} while (retry > 0);
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if (!retry)
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dev_err(dev, "Clear CK_OUT_EN timedout\n");
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/* Set CK_OUT_EN */
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setbits_le32(®s->sdcc_hc_dll_config, SDCC_DLL_CONFIG_CK_OUT_EN);
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/* Wait for CK_OUT_EN set */
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retry = 1000;
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do {
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val = readl(®s->sdcc_hc_dll_config);
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val &= SDCC_DLL_CONFIG_CK_OUT_EN;
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if (val)
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break;
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mdelay(1);
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retry--;
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} while (retry > 0);
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if (!retry)
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dev_err(dev, "Set CK_OUT_EN timedout\n");
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/* Set DDR_CAL_EN */
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setbits_le32(®s->sdcc_hc_dll_config2, SDCC_DLL_CONFIG2_DDR_CAL_EN);
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clrbits_le32(®s->sdcc_hc_dll_config2,
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SDCC_DLL_CONFIG2_DLL_CLOCK_DIS);
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clrsetbits_le32(®s->sdcc_hc_dll_config2,
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SDCC_DLL_CONFIG2_MCLK_FREQ_CALC, 0x1A << 10);
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clrsetbits_le32(®s->sdcc_hc_dll_config2,
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SDCC_DLL_CONFIG2_DDR_TRAFFIC_INIT_SEL, BIT(2));
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setbits_le32(®s->sdcc_hc_dll_config2,
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SDCC_DLL_CONFIG2_DDR_TRAFFIC_INIT_SW);
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return 0;
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}
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static int ethqos_rgmii_macro_init(struct udevice *dev,
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struct dwmac_rgmii_regs *regs,
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unsigned long speed)
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{
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/* Disable loopback mode */
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clrbits_le32(®s->io_macro_config2,
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RGMII_CONFIG2_TX_TO_RX_LOOPBACK_EN);
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/* Select RGMII, write 0 to interface select */
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clrbits_le32(®s->io_macro_config, RGMII_CONFIG_INTF_SEL);
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switch (speed) {
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case SPEED_1000:
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setbits_le32(®s->io_macro_config, RGMII_CONFIG_DDR_MODE);
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clrbits_le32(®s->io_macro_config,
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RGMII_CONFIG_BYPASS_TX_ID_EN);
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setbits_le32(®s->io_macro_config,
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RGMII_CONFIG_POS_NEG_DATA_SEL);
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setbits_le32(®s->io_macro_config, RGMII_CONFIG_PROG_SWAP);
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clrbits_le32(®s->io_macro_config2,
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RGMII_CONFIG2_DATA_DIVIDE_CLK_SEL);
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setbits_le32(®s->io_macro_config2,
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RGMII_CONFIG2_TX_CLK_PHASE_SHIFT_EN);
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clrbits_le32(®s->io_macro_config2,
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RGMII_CONFIG2_RSVD_CONFIG15);
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setbits_le32(®s->io_macro_config2,
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RGMII_CONFIG2_RX_PROG_SWAP);
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/* Set PRG_RCLK_DLY to 57 for 1.8 ns delay */
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clrsetbits_le32(®s->sdcc_hc_ddr_config,
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SDCC_DDR_CONFIG_PRG_RCLK_DLY, 57);
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setbits_le32(®s->sdcc_hc_ddr_config, SDCC_DDR_CONFIG_PRG_DLY_EN);
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setbits_le32(®s->io_macro_config, RGMII_CONFIG_LOOPBACK_EN);
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break;
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case SPEED_100:
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setbits_le32(®s->io_macro_config, RGMII_CONFIG_DDR_MODE);
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setbits_le32(®s->io_macro_config,
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RGMII_CONFIG_BYPASS_TX_ID_EN);
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clrbits_le32(®s->io_macro_config,
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RGMII_CONFIG_POS_NEG_DATA_SEL);
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clrbits_le32(®s->io_macro_config, RGMII_CONFIG_PROG_SWAP);
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clrsetbits_le32(®s->io_macro_config,
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RGMII_CONFIG_MAX_SPD_PRG_2, BIT(6));
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clrbits_le32(®s->io_macro_config2,
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RGMII_CONFIG2_DATA_DIVIDE_CLK_SEL);
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setbits_le32(®s->io_macro_config2,
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RGMII_CONFIG2_TX_CLK_PHASE_SHIFT_EN);
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clrbits_le32(®s->io_macro_config2,
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RGMII_CONFIG2_RSVD_CONFIG15);
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clrbits_le32(®s->io_macro_config2,
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RGMII_CONFIG2_RX_PROG_SWAP);
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/* Write 0x5 to PRG_RCLK_DLY_CODE */
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clrsetbits_le32(®s->sdcc_hc_ddr_config,
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SDCC_DDR_CONFIG_EXT_PRG_RCLK_DLY_CODE,
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(BIT(29) | BIT(27)));
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setbits_le32(®s->sdcc_hc_ddr_config,
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SDCC_DDR_CONFIG_EXT_PRG_RCLK_DLY);
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setbits_le32(®s->sdcc_hc_ddr_config,
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SDCC_DDR_CONFIG_EXT_PRG_RCLK_DLY_EN);
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setbits_le32(®s->io_macro_config, RGMII_CONFIG_LOOPBACK_EN);
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break;
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case SPEED_10:
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setbits_le32(®s->io_macro_config, RGMII_CONFIG_DDR_MODE);
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setbits_le32(®s->io_macro_config,
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RGMII_CONFIG_BYPASS_TX_ID_EN);
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clrbits_le32(®s->io_macro_config,
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RGMII_CONFIG_POS_NEG_DATA_SEL);
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clrbits_le32(®s->io_macro_config, RGMII_CONFIG_PROG_SWAP);
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clrsetbits_le32(®s->io_macro_config,
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RGMII_CONFIG_MAX_SPD_PRG_9,
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BIT(12) | GENMASK(9, 8));
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clrbits_le32(®s->io_macro_config2,
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RGMII_CONFIG2_DATA_DIVIDE_CLK_SEL);
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clrbits_le32(®s->io_macro_config2,
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RGMII_CONFIG2_TX_CLK_PHASE_SHIFT_EN);
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clrbits_le32(®s->io_macro_config2,
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RGMII_CONFIG2_RSVD_CONFIG15);
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clrbits_le32(®s->io_macro_config2,
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RGMII_CONFIG2_RX_PROG_SWAP);
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/* Write 0x5 to PRG_RCLK_DLY_CODE */
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clrsetbits_le32(®s->sdcc_hc_ddr_config,
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SDCC_DDR_CONFIG_EXT_PRG_RCLK_DLY_CODE,
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(BIT(29) | BIT(27)));
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setbits_le32(®s->sdcc_hc_ddr_config,
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SDCC_DDR_CONFIG_EXT_PRG_RCLK_DLY);
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setbits_le32(®s->sdcc_hc_ddr_config,
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SDCC_DDR_CONFIG_EXT_PRG_RCLK_DLY_EN);
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setbits_le32(®s->io_macro_config, RGMII_CONFIG_LOOPBACK_EN);
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break;
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default:
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dev_err(dev, "Invalid speed %ld\n", speed);
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return -EINVAL;
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}
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return 0;
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}
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static int ethqos_configure(struct udevice *dev,
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struct dwmac_rgmii_regs *regs,
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unsigned long speed)
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{
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unsigned int retry = 1000;
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/* Reset to POR values and enable clk */
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writel(emac_v2_3_0_por.io_macro_config, ®s->io_macro_config);
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writel(emac_v2_3_0_por.sdcc_hc_dll_config, ®s->sdcc_hc_dll_config);
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writel(emac_v2_3_0_por.sdcc_hc_ddr_config, ®s->sdcc_hc_ddr_config);
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writel(emac_v2_3_0_por.sdcc_hc_dll_config2, ®s->sdcc_hc_dll_config2);
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writel(emac_v2_3_0_por.sdcc_usr_ctl, ®s->sdcc_usr_ctl);
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writel(emac_v2_3_0_por.io_macro_config2, ®s->io_macro_config2);
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ethqos_set_func_clk_en(regs);
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/* Initialize the DLL first */
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/* Set DLL_RST */
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setbits_le32(®s->sdcc_hc_dll_config, SDCC_DLL_CONFIG_DLL_RST);
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/* Set PDN */
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setbits_le32(®s->sdcc_hc_dll_config, SDCC_DLL_CONFIG_PDN);
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/* Clear DLL_RST */
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clrbits_le32(®s->sdcc_hc_dll_config, SDCC_DLL_CONFIG_DLL_RST);
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/* Clear PDN */
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clrbits_le32(®s->sdcc_hc_dll_config, SDCC_DLL_CONFIG_PDN);
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if (speed == SPEED_1000) {
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/* Set DLL_EN */
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setbits_le32(®s->sdcc_hc_dll_config, SDCC_DLL_CONFIG_DLL_EN);
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/* Set CK_OUT_EN */
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setbits_le32(®s->sdcc_hc_dll_config,
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SDCC_DLL_CONFIG_CK_OUT_EN);
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/* Set USR_CTL bit 26 with mask of 3 bits */
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clrsetbits_le32(®s->sdcc_usr_ctl, GENMASK(26, 24), BIT(26));
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/* wait for DLL LOCK */
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do {
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mdelay(1);
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if (readl(®s->sdc4_status) & SDC4_STATUS_DLL_LOCK)
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break;
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retry--;
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} while (retry > 0);
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if (!retry)
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dev_err(dev, "Timeout while waiting for DLL lock\n");
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ethqos_dll_configure(dev, regs);
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}
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ethqos_rgmii_macro_init(dev, regs, speed);
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return 0;
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}
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static void ethqos_rgmii_dump(struct udevice *dev,
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struct dwmac_rgmii_regs *regs)
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{
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dev_dbg(dev, "Rgmii register dump\n");
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dev_dbg(dev, "RGMII_IO_MACRO_CONFIG: %08x\n",
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readl(®s->io_macro_config));
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dev_dbg(dev, "SDCC_HC_REG_DLL_CONFIG: %08x\n",
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readl(®s->sdcc_hc_dll_config));
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dev_dbg(dev, "SDCC_HC_REG_DDR_CONFIG: %08x\n",
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readl(®s->sdcc_hc_ddr_config));
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dev_dbg(dev, "SDCC_HC_REG_DLL_CONFIG2: %08x\n",
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readl(®s->sdcc_hc_dll_config2));
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dev_dbg(dev, "SDC4_STATUS: %08x\n",
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readl(®s->sdc4_status));
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dev_dbg(dev, "SDCC_USR_CTL: %08x\n",
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readl(®s->sdcc_usr_ctl));
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dev_dbg(dev, "RGMII_IO_MACRO_CONFIG2: %08x\n",
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readl(®s->io_macro_config2));
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dev_dbg(dev, "RGMII_IO_MACRO_DEBUG1: %08x\n",
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readl(®s->io_macro_debug1));
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dev_dbg(dev, "EMAC_SYSTEM_LOW_POWER_DEBUG: %08x\n",
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readl(®s->emac_sys_low_power_dbg));
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}
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static int qcom_eqos_rgmii_set_speed(struct udevice *dev,
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void *rgmii_regs,
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unsigned long speed)
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{
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int ret;
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ethqos_rgmii_dump(dev, rgmii_regs);
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ret = ethqos_configure(dev, rgmii_regs, speed);
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if (ret)
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return ret;
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ethqos_rgmii_dump(dev, rgmii_regs);
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return 0;
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}
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static int qcom_eqos_rgmii_reset(struct udevice *dev, void *rgmii_regs)
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{
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ethqos_set_func_clk_en(rgmii_regs);
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return 0;
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}
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static int eqos_start_clks_qcom(struct udevice *dev)
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{
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if (IS_ENABLED(CONFIG_CLK)) {
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struct clk_bulk clocks;
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int ret;
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ret = clk_get_bulk(dev, &clocks);
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if (ret)
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return ret;
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ret = clk_enable_bulk(&clocks);
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if (ret)
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return ret;
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}
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debug("%s: OK\n", __func__);
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return 0;
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}
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static int eqos_stop_clks_qcom(struct udevice *dev)
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{
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if (IS_ENABLED(CONFIG_CLK)) {
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struct clk_bulk clocks;
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int ret;
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ret = clk_get_bulk(dev, &clocks);
|
|
if (ret)
|
|
return ret;
|
|
|
|
ret = clk_disable_bulk(&clocks);
|
|
if (ret)
|
|
return ret;
|
|
}
|
|
|
|
debug("%s: OK\n", __func__);
|
|
return 0;
|
|
}
|
|
|
|
static int eqos_start_resets_qcom(struct udevice *dev)
|
|
{
|
|
struct eqos_priv *eqos = dev_get_priv(dev);
|
|
int ret;
|
|
|
|
debug("%s(dev=%p):\n", __func__, dev);
|
|
|
|
if (!eqos->phy) {
|
|
ret = dm_gpio_set_value(&eqos->phy_reset_gpio, 0);
|
|
if (ret < 0) {
|
|
pr_err("dm_gpio_set_value(phy_reset, assert) failed: %d", ret);
|
|
return ret;
|
|
}
|
|
|
|
udelay(eqos->reset_delays[0]);
|
|
|
|
ret = dm_gpio_set_value(&eqos->phy_reset_gpio, 1);
|
|
if (ret < 0) {
|
|
pr_err("dm_gpio_set_value(phy_reset, deassert) failed: %d", ret);
|
|
return ret;
|
|
}
|
|
|
|
udelay(eqos->reset_delays[1]);
|
|
|
|
ret = dm_gpio_set_value(&eqos->phy_reset_gpio, 0);
|
|
if (ret < 0) {
|
|
pr_err("dm_gpio_set_value(phy_reset, deassert) failed: %d", ret);
|
|
return ret;
|
|
}
|
|
|
|
udelay(eqos->reset_delays[2]);
|
|
}
|
|
|
|
ret = reset_deassert(&eqos->reset_ctl);
|
|
if (ret < 0) {
|
|
pr_err("reset_deassert() failed: %d", ret);
|
|
return ret;
|
|
}
|
|
|
|
ret = qcom_eqos_rgmii_reset(dev, eqos->eqos_qcom_rgmii_regs);
|
|
if (ret < 0) {
|
|
pr_err("qcom rgmii_reset failed: %d", ret);
|
|
return ret;
|
|
}
|
|
|
|
debug("%s: OK\n", __func__);
|
|
return 0;
|
|
}
|
|
|
|
/* Clock rates */
|
|
#define RGMII_1000_NOM_CLK_FREQ (250 * 1000 * 1000UL)
|
|
#define RGMII_ID_MODE_100_LOW_SVS_CLK_FREQ (50 * 1000 * 1000UL)
|
|
#define RGMII_ID_MODE_10_LOW_SVS_CLK_FREQ (5 * 1000 * 1000UL)
|
|
|
|
static int eqos_set_tx_clk_speed_qcom(struct udevice *dev)
|
|
{
|
|
struct eqos_priv *eqos = dev_get_priv(dev);
|
|
ulong rate;
|
|
int ret;
|
|
|
|
debug("%s(dev=%p):\n", __func__, dev);
|
|
|
|
switch (eqos->phy->speed) {
|
|
case SPEED_1000:
|
|
rate = RGMII_1000_NOM_CLK_FREQ;
|
|
break;
|
|
case SPEED_100:
|
|
rate = RGMII_ID_MODE_100_LOW_SVS_CLK_FREQ;
|
|
break;
|
|
case SPEED_10:
|
|
rate = RGMII_ID_MODE_10_LOW_SVS_CLK_FREQ;
|
|
break;
|
|
default:
|
|
pr_err("invalid speed %d", eqos->phy->speed);
|
|
return -EINVAL;
|
|
}
|
|
|
|
ret = clk_set_rate(&eqos->clk_tx, rate);
|
|
if (ret < 0) {
|
|
pr_err("clk_set_rate(tx_clk, %lu) failed: %d", rate, ret);
|
|
return ret;
|
|
}
|
|
|
|
ret = qcom_eqos_rgmii_set_speed(dev, eqos->eqos_qcom_rgmii_regs,
|
|
eqos->phy->speed);
|
|
if (ret < 0) {
|
|
pr_err("qcom set_speed: %d, failed: %d", eqos->phy->speed, ret);
|
|
return ret;
|
|
}
|
|
|
|
return 0;
|
|
}
|
|
|
|
static int eqos_probe_resources_qcom(struct udevice *dev)
|
|
{
|
|
struct eqos_priv *eqos = dev_get_priv(dev);
|
|
phy_interface_t interface;
|
|
int reset_flags = GPIOD_IS_OUT;
|
|
int ret;
|
|
|
|
debug("%s(dev=%p):\n", __func__, dev);
|
|
|
|
interface = eqos->config->interface(dev);
|
|
|
|
if (interface == PHY_INTERFACE_MODE_NA) {
|
|
pr_err("Invalid PHY interface\n");
|
|
return -EINVAL;
|
|
}
|
|
|
|
eqos->max_speed = dev_read_u32_default(dev, "max-speed", 0);
|
|
|
|
eqos->tx_fifo_sz = dev_read_u32_default(dev, "tx-fifo-depth", 0);
|
|
eqos->rx_fifo_sz = dev_read_u32_default(dev, "rx-fifo-depth", 0);
|
|
|
|
ret = reset_get_by_name(dev, "emac", &eqos->reset_ctl);
|
|
if (ret) {
|
|
pr_err("reset_get_by_name(rst) failed: %d", ret);
|
|
return ret;
|
|
}
|
|
|
|
if (dev_read_bool(dev, "snps,reset-active-low"))
|
|
reset_flags |= GPIOD_ACTIVE_LOW;
|
|
|
|
ret = gpio_request_by_name(dev, "snps,reset-gpio", 0,
|
|
&eqos->phy_reset_gpio, reset_flags);
|
|
if (ret == 0) {
|
|
ret = dev_read_u32_array(dev, "snps,reset-delays-us",
|
|
eqos->reset_delays, 3);
|
|
} else if (ret == -ENOENT) {
|
|
ret = 0;
|
|
}
|
|
|
|
eqos->eqos_qcom_rgmii_regs = (void *)dev_read_addr_name(dev, "rgmii");
|
|
if ((fdt_addr_t)eqos->eqos_qcom_rgmii_regs == FDT_ADDR_T_NONE) {
|
|
pr_err("Invalid RGMII address\n");
|
|
return -EINVAL;
|
|
}
|
|
|
|
ret = clk_get_by_name(dev, "rgmii", &eqos->clk_tx);
|
|
if (ret) {
|
|
pr_err("clk_get_by_name(tx) failed: %d", ret);
|
|
return -EINVAL;
|
|
}
|
|
|
|
debug("%s: OK\n", __func__);
|
|
return 0;
|
|
}
|
|
|
|
static int eqos_remove_resources_qcom(struct udevice *dev)
|
|
{
|
|
struct eqos_priv *eqos = dev_get_priv(dev);
|
|
|
|
debug("%s(dev=%p):\n", __func__, dev);
|
|
|
|
dm_gpio_free(dev, &eqos->phy_reset_gpio);
|
|
reset_free(&eqos->reset_ctl);
|
|
|
|
debug("%s: OK\n", __func__);
|
|
return 0;
|
|
}
|
|
|
|
static struct eqos_ops eqos_qcom_ops = {
|
|
.eqos_inval_desc = eqos_inval_desc_generic,
|
|
.eqos_flush_desc = eqos_flush_desc_generic,
|
|
.eqos_inval_buffer = eqos_inval_buffer_generic,
|
|
.eqos_flush_buffer = eqos_flush_buffer_generic,
|
|
.eqos_probe_resources = eqos_probe_resources_qcom,
|
|
.eqos_remove_resources = eqos_remove_resources_qcom,
|
|
.eqos_stop_resets = eqos_null_ops,
|
|
.eqos_start_resets = eqos_start_resets_qcom,
|
|
.eqos_stop_clks = eqos_stop_clks_qcom,
|
|
.eqos_start_clks = eqos_start_clks_qcom,
|
|
.eqos_calibrate_pads = eqos_null_ops,
|
|
.eqos_disable_calibration = eqos_null_ops,
|
|
.eqos_set_tx_clk_speed = eqos_set_tx_clk_speed_qcom,
|
|
.eqos_get_enetaddr = eqos_null_ops,
|
|
};
|
|
|
|
struct eqos_config __maybe_unused eqos_qcom_config = {
|
|
.reg_access_always_ok = false,
|
|
.mdio_wait = 10,
|
|
.swr_wait = 50,
|
|
.config_mac = EQOS_MAC_RXQ_CTRL0_RXQ0EN_ENABLED_DCB,
|
|
.config_mac_mdio = EQOS_MAC_MDIO_ADDRESS_CR_250_300,
|
|
.axi_bus_width = EQOS_AXI_WIDTH_64,
|
|
.interface = dev_read_phy_mode,
|
|
.ops = &eqos_qcom_ops
|
|
};
|