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This driver is adapted from linux drivers/reset/reset-stm32.c It's compatible with STM32 F4/F7/H7 SoCs. This driver doesn't implement .of_match as it's binded by MFD RCC driver. To add support for each SoC family, a SoC's specific include/dt-binfings/mfd/stm32xx-rcc.h file must be added. This patch only includes stm32h7-rcc.h dedicated for STM32H7 SoCs. Other SoCs support will be added in the future. Signed-off-by: Patrice Chotard <patrice.chotard@st.com> Reviewed-by: Simon Glass <sjg@chromium.org>
139 lines
4.1 KiB
C
139 lines
4.1 KiB
C
/*
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* This header provides constants for the STM32H7 RCC IP
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*/
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#ifndef _DT_BINDINGS_MFD_STM32H7_RCC_H
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#define _DT_BINDINGS_MFD_STM32H7_RCC_H
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/* AHB3 */
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#define STM32H7_RCC_AHB3_MDMA 0
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#define STM32H7_RCC_AHB3_DMA2D 4
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#define STM32H7_RCC_AHB3_JPGDEC 5
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#define STM32H7_RCC_AHB3_FMC 12
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#define STM32H7_RCC_AHB3_QUADSPI 14
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#define STM32H7_RCC_AHB3_SDMMC1 16
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#define STM32H7_RCC_AHB3_CPU1 31
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#define STM32H7_AHB3_RESET(bit) (STM32H7_RCC_AHB3_##bit + (0x7C * 8))
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/* AHB1 */
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#define STM32H7_RCC_AHB1_DMA1 0
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#define STM32H7_RCC_AHB1_DMA2 1
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#define STM32H7_RCC_AHB1_ADC12 5
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#define STM32H7_RCC_AHB1_ART 14
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#define STM32H7_RCC_AHB1_ETH1MAC 15
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#define STM32H7_RCC_AHB1_USB1OTG 25
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#define STM32H7_RCC_AHB1_USB2OTG 27
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#define STM32H7_RCC_AHB1_CPU2 31
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#define STM32H7_AHB1_RESET(bit) (STM32H7_RCC_AHB1_##bit + (0x80 * 8))
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/* AHB2 */
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#define STM32H7_RCC_AHB2_CAMITF 0
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#define STM32H7_RCC_AHB2_CRYPT 4
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#define STM32H7_RCC_AHB2_HASH 5
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#define STM32H7_RCC_AHB2_RNG 6
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#define STM32H7_RCC_AHB2_SDMMC2 9
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#define STM32H7_AHB2_RESET(bit) (STM32H7_RCC_AHB2_##bit + (0x84 * 8))
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/* AHB4 */
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#define STM32H7_RCC_AHB4_GPIOA 0
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#define STM32H7_RCC_AHB4_GPIOB 1
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#define STM32H7_RCC_AHB4_GPIOC 2
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#define STM32H7_RCC_AHB4_GPIOD 3
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#define STM32H7_RCC_AHB4_GPIOE 4
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#define STM32H7_RCC_AHB4_GPIOF 5
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#define STM32H7_RCC_AHB4_GPIOG 6
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#define STM32H7_RCC_AHB4_GPIOH 7
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#define STM32H7_RCC_AHB4_GPIOI 8
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#define STM32H7_RCC_AHB4_GPIOJ 9
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#define STM32H7_RCC_AHB4_GPIOK 10
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#define STM32H7_RCC_AHB4_CRC 19
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#define STM32H7_RCC_AHB4_BDMA 21
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#define STM32H7_RCC_AHB4_ADC3 24
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#define STM32H7_RCC_AHB4_HSEM 25
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#define STM32H7_AHB4_RESET(bit) (STM32H7_RCC_AHB4_##bit + (0x88 * 8))
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/* APB3 */
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#define STM32H7_RCC_APB3_LTDC 3
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#define STM32H7_RCC_APB3_DSI 4
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#define STM32H7_APB3_RESET(bit) (STM32H7_RCC_APB3_##bit + (0x8C * 8))
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/* APB1L */
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#define STM32H7_RCC_APB1L_TIM2 0
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#define STM32H7_RCC_APB1L_TIM3 1
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#define STM32H7_RCC_APB1L_TIM4 2
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#define STM32H7_RCC_APB1L_TIM5 3
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#define STM32H7_RCC_APB1L_TIM6 4
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#define STM32H7_RCC_APB1L_TIM7 5
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#define STM32H7_RCC_APB1L_TIM12 6
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#define STM32H7_RCC_APB1L_TIM13 7
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#define STM32H7_RCC_APB1L_TIM14 8
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#define STM32H7_RCC_APB1L_LPTIM1 9
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#define STM32H7_RCC_APB1L_SPI2 14
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#define STM32H7_RCC_APB1L_SPI3 15
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#define STM32H7_RCC_APB1L_SPDIF_RX 16
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#define STM32H7_RCC_APB1L_USART2 17
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#define STM32H7_RCC_APB1L_USART3 18
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#define STM32H7_RCC_APB1L_UART4 19
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#define STM32H7_RCC_APB1L_UART5 20
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#define STM32H7_RCC_APB1L_I2C1 21
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#define STM32H7_RCC_APB1L_I2C2 22
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#define STM32H7_RCC_APB1L_I2C3 23
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#define STM32H7_RCC_APB1L_HDMICEC 27
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#define STM32H7_RCC_APB1L_DAC12 29
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#define STM32H7_RCC_APB1L_USART7 30
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#define STM32H7_RCC_APB1L_USART8 31
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#define STM32H7_APB1L_RESET(bit) (STM32H7_RCC_APB1L_##bit + (0x90 * 8))
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/* APB1H */
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#define STM32H7_RCC_APB1H_CRS 1
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#define STM32H7_RCC_APB1H_SWP 2
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#define STM32H7_RCC_APB1H_OPAMP 4
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#define STM32H7_RCC_APB1H_MDIOS 5
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#define STM32H7_RCC_APB1H_FDCAN 8
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#define STM32H7_APB1H_RESET(bit) (STM32H7_RCC_APB1H_##bit + (0x94 * 8))
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/* APB2 */
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#define STM32H7_RCC_APB2_TIM1 0
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#define STM32H7_RCC_APB2_TIM8 1
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#define STM32H7_RCC_APB2_USART1 4
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#define STM32H7_RCC_APB2_USART6 5
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#define STM32H7_RCC_APB2_SPI1 12
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#define STM32H7_RCC_APB2_SPI4 13
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#define STM32H7_RCC_APB2_TIM15 16
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#define STM32H7_RCC_APB2_TIM16 17
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#define STM32H7_RCC_APB2_TIM17 18
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#define STM32H7_RCC_APB2_SPI5 20
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#define STM32H7_RCC_APB2_SAI1 22
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#define STM32H7_RCC_APB2_SAI2 23
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#define STM32H7_RCC_APB2_SAI3 24
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#define STM32H7_RCC_APB2_DFSDM1 28
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#define STM32H7_RCC_APB2_HRTIM 29
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#define STM32H7_APB2_RESET(bit) (STM32H7_RCC_APB2_##bit + (0x98 * 8))
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/* APB4 */
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#define STM32H7_RCC_APB4_SYSCFG 1
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#define STM32H7_RCC_APB4_LPUART1 3
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#define STM32H7_RCC_APB4_SPI6 5
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#define STM32H7_RCC_APB4_I2C4 7
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#define STM32H7_RCC_APB4_LPTIM2 9
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#define STM32H7_RCC_APB4_LPTIM3 10
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#define STM32H7_RCC_APB4_LPTIM4 11
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#define STM32H7_RCC_APB4_LPTIM5 12
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#define STM32H7_RCC_APB4_COMP12 14
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#define STM32H7_RCC_APB4_VREF 15
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#define STM32H7_RCC_APB4_SAI4 21
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#define STM32H7_RCC_APB4_TMPSENS 26
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#define STM32H7_APB4_RESET(bit) (STM32H7_RCC_APB4_##bit + (0x9C * 8))
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#endif /* _DT_BINDINGS_MFD_STM32H7_RCC_H */
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