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6924bc7ca2
Currently, the DDR type is retrieved by iteracting inside an array of possible DDR types. This may take saveral attempts, which slows the overall U-Boot process and does not provide a good user experience: U-Boot SPL 2021.07 (Feb 28 2022 - 06:39:32 +0000) DDRINFO: Cfg attempt: [ 1/6 ] DDRINFO(M): mr5-8 [ 0xff000010 ] DDRINFO(T): mr5-8 [ 0x5000010 ] resetting ... U-Boot SPL 2021.07 (Feb 28 2022 - 06:39:32 +0000) DDRINFO: Cfg attempt: [ 2/6 ] DDRINFO(M): mr5-8 [ 0xff000010 ] DDRINFO(T): mr5-8 [ 0x1061010 ] resetting ... U-Boot SPL 2021.07 (Feb 28 2022 - 06:39:32 +0000) DDRINFO: Cfg attempt: [ 3/6 ] DDRINFO(M): mr5-8 [ 0xff000010 ] DDRINFO(T): mr5-8 [ 0xff000010 ] Normal Boot WDT: Not starting Trying to boot from MMC2 NOTICE: BL31: v2.5(release):v2.5 NOTICE: BL31: Built : 07:12:44, Jan 24 2022 Improve the boot time by retrieving the correct DDR information from the EEPROM: U-Boot SPL 2022.04-rc4-00045-g6d02bc40d58c (Mar 19 2022 - 08:22:29 -0300) DDRINFO(D): Kingston 4096G DDRINFO(M): mr5-8 [ 0xff000010 ] DDRINFO(E): mr5-8 [ 0xff000010 ] Normal Boot WDT: Started watchdog@30280000 with servicing (60s timeout) Trying to boot from MMC2 NOTICE: BL31: v2.5(release):v2.5 NOTICE: BL31: Built : 22:28:11, Mar 15 2022 Based on the original code from Compulab's U-Boot. Tested on a imx8mm-cl-iot-gate board populated with 4GB of RAM. Signed-off-by: Fabio Estevam <festevam@denx.de>
32 lines
684 B
C
32 lines
684 B
C
/* SPDX-License-Identifier: GPL-2.0+ */
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/*
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* Copyright 2017 NXP
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* Copyright 2020 Linaro
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*
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*/
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#ifndef __COMPULAB_DDR_H__
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#define __COMPULAB_DDR_H__
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extern struct dram_timing_info ucm_dram_timing_ff020008;
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extern struct dram_timing_info ucm_dram_timing_ff000110;
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extern struct dram_timing_info ucm_dram_timing_01061010;
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void spl_dram_init_compulab(void);
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#define TCM_DATA_CFG 0x7e0000
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struct lpddr4_tcm_desc {
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unsigned int size;
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unsigned int sign;
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unsigned int index;
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unsigned int count;
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};
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u32 cl_eeprom_get_ddrinfo(void);
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u32 cl_eeprom_set_ddrinfo(u32 ddrinfo);
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u32 cl_eeprom_get_subind(void);
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u32 cl_eeprom_set_subind(u32 subind);
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u32 cl_eeprom_get_osize(void);
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#endif
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