Benoît Thébaudeau ada02b8463 imx: mx6q DDR3 init: Fix SDE_to_RST ...

MMDC1_MDOR.SDE_to_RST should be set to 200 µs according to the JEDEC
specification for DDR3. With a cycle of 15.258 µs, this gives 14 cycles encoded
as 0x10 for the bit-field MMDC1_MDOR[13:8].

Signed-off-by: Benoît Thébaudeau <benoit.thebaudeau@advansee.com>

2013-02-12 13:52:30 +01:00

..

mx6q_4x_mt41j128.cfg

imx: mx6q DDR3 init: Fix SDE_to_RST

2013-02-12 13:52:30 +01:00