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	When U-Boot started using SPDX tags we were among the early adopters and there weren't a lot of other examples to borrow from. So we picked the area of the file that usually had a full license text and replaced it with an appropriate SPDX-License-Identifier: entry. Since then, the Linux Kernel has adopted SPDX tags and they place it as the very first line in a file (except where shebangs are used, then it's second line) and with slightly different comment styles than us. In part due to community overlap, in part due to better tag visibility and in part for other minor reasons, switch over to that style. This commit changes all instances where we have a single declared license in the tag as both the before and after are identical in tag contents. There's also a few places where I found we did not have a tag and have introduced one. Signed-off-by: Tom Rini <trini@konsulko.com>
		
			
				
	
	
		
			402 lines
		
	
	
		
			7.9 KiB
		
	
	
	
		
			C
		
	
	
	
	
	
			
		
		
	
	
			402 lines
		
	
	
		
			7.9 KiB
		
	
	
	
		
			C
		
	
	
	
	
	
| // SPDX-License-Identifier: GPL-2.0+
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| /*
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|  * (C) Copyright 2002
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|  * Daniel Engström, Omicron Ceti AB <daniel@omicron.se>.
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|  */
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| 
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| /*
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|  * Based on sc520cdp.c from rolo 1.6:
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|  *----------------------------------------------------------------------
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|  * (C) Copyright 2000
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|  * Sysgo Real-Time Solutions GmbH
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|  * Klein-Winternheim, Germany
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|  *----------------------------------------------------------------------
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|  */
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| 
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| #include <config.h>
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| 
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| #include <common.h>
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| #include <asm/io.h>
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| #include <ali512x.h>
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| 
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| 
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| /* ALI M5123 Logical device numbers:
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|  * 0 FDC
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|  * 1 unused?
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|  * 2 unused?
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|  * 3 lpt
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|  * 4 UART1
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|  * 5 UART2
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|  * 6 RTC
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|  * 7 mouse/kbd
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|  * 8 CIO
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|  */
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| 
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| /*
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|  ************************************************************
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|  *  Some access primitives for the ALi chip:                *
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|  ************************************************************
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|  */
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| 
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| static void ali_write(u8 index, u8 value)
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| {
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| 	/* write an arbirary register */
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| 	outb(index, ALI_INDEX);
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| 	outb(value, ALI_DATA);
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| }
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| 
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| #if 0
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| static int ali_read(u8 index)
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| {
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| 	outb(index, ALI_INDEX);
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| 	return inb(ALI_DATA);
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| }
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| #endif
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| 
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| #define ALI_OPEN() \
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| 	outb(0x51, ALI_INDEX); \
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| 	outb(0x23, ALI_INDEX)
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| 
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| 
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| #define ALI_CLOSE() \
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| 	outb(0xbb, ALI_INDEX)
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| 
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| /* Select a logical device */
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| #define ALI_SELDEV(dev)	\
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| 	ali_write(0x07, dev)
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| 
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| 
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| void ali512x_init(void)
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| {
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| 	ALI_OPEN();
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| 
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| 	ali_write(0x02, 0x01);	/* soft reset */
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| 	ali_write(0x03, 0x03);	/* disable access to CIOs */
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| 	ali_write(0x22, 0x00);	/* disable direct powerdown */
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| 	ali_write(0x23, 0x00);	/* disable auto powerdown */
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| 	ali_write(0x24, 0x00);	/* IR 8 is active hi, pin26 is PDIR */
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| 
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| 	ALI_CLOSE();
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| }
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| 
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| void ali512x_set_fdc(int enabled, u16 io, u8 irq, u8 dma_channel)
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| {
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| 	ALI_OPEN();
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| 	ALI_SELDEV(0);
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| 
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| 	ali_write(0x30, enabled?1:0);
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| 	if (enabled) {
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| 		ali_write(0x60, io >> 8);
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| 		ali_write(0x61, io & 0xff);
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| 		ali_write(0x70, irq);
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| 		ali_write(0x74, dma_channel);
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| 
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| 		/* AT mode, no drive swap */
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| 		ali_write(0xf0, 0x08);
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| 		ali_write(0xf1, 0x00);
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| 		ali_write(0xf2, 0xff);
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| 		ali_write(0xf4, 0x00);
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| 	}
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| 	ALI_CLOSE();
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| }
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| 
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| 
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| void ali512x_set_pp(int enabled, u16 io, u8 irq, u8 dma_channel)
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| {
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| 	ALI_OPEN();
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| 	ALI_SELDEV(3);
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| 
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| 	ali_write(0x30, enabled?1:0);
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| 	if (enabled) {
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| 		ali_write(0x60, io >> 8);
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| 		ali_write(0x61, io & 0xff);
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| 		ali_write(0x70, irq);
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| 		ali_write(0x74, dma_channel);
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| 
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| 		/* mode: EPP 1.9, ECP FIFO threshold = 7, IRQ active low */
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| 		ali_write(0xf0, 0xbc);
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| 		/* 12 MHz, Burst DMA in ECP */
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| 		ali_write(0xf1, 0x05);
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| 	}
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| 	ALI_CLOSE();
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| 
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| }
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| 
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| void ali512x_set_uart(int enabled, int index, u16 io, u8 irq)
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| {
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| 	ALI_OPEN();
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| 	ALI_SELDEV(index?5:4);
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| 
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| 	ali_write(0x30, enabled?1:0);
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| 	if (enabled) {
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| 		ali_write(0x60, io >> 8);
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| 		ali_write(0x61, io & 0xff);
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| 		ali_write(0x70, irq);
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| 
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| 		ali_write(0xf0, 0x00);
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| 		ali_write(0xf1, 0x00);
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| 
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| 		/* huh? write 0xf2 twice - a typo in rolo
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| 		 * or some secret ali errata? Who knows?
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| 		 */
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| 		if (index) {
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| 			ali_write(0xf2, 0x00);
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| 		}
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| 		ali_write(0xf2, 0x0c);
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| 	}
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| 	ALI_CLOSE();
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| 
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| }
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| 
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| void ali512x_set_uart2_irda(int enabled)
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| {
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| 	ALI_OPEN();
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| 	ALI_SELDEV(5);
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| 
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| 	ali_write(0xf1, enabled?0x48:0x00); /* fullduplex IrDa */
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| 	ALI_CLOSE();
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| 
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| }
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| 
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| void ali512x_set_rtc(int enabled, u16 io, u8 irq)
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| {
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| 	ALI_OPEN();
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| 	ALI_SELDEV(6);
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| 
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| 	ali_write(0x30, enabled?1:0);
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| 	if (enabled) {
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| 		ali_write(0x60, io >> 8);
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| 		ali_write(0x61, io & 0xff);
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| 		ali_write(0x70, irq);
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| 
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| 		ali_write(0xf0, 0x00);
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| 	}
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| 	ALI_CLOSE();
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| }
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| 
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| void ali512x_set_kbc(int enabled, u8 kbc_irq, u8 mouse_irq)
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| {
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| 	ALI_OPEN();
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| 	ALI_SELDEV(7);
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| 
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| 	ali_write(0x30, enabled?1:0);
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| 	if (enabled) {
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| 		ali_write(0x70, kbc_irq);
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| 		ali_write(0x72, mouse_irq);
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| 
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| 		ali_write(0xf0, 0x00);
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| 	}
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| 	ALI_CLOSE();
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| }
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| 
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| 
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| /* Common I/O
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|  *
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|  * (This descripotsion is base on several incompete sources
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|  *  since I have not been able to obtain any datasheet for the device
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|  *  there may be some mis-understandings burried in here.
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|  *  -- Daniel daniel@omicron.se)
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|  *
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|  * There are 22 CIO pins numbered
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|  * 10-17
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|  * 20-25
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|  * 30-37
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|  *
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|  * 20-24 are dedicated CIO pins, the other 17 are muliplexed with
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|  * other functions.
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|  *
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|  *           Secondary
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|  * CIO Pin   Function    Decription
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|  * =======================================================
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|  * CIO10     IRQIN1      Interrupt input 1?
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|  * CIO11     IRQIN2      Interrupt input 2?
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|  * CIO12     IRRX        IrDa Receive
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|  * CIO13     IRTX        IrDa Transmit
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|  * CIO14     P21         KBC P21 fucntion
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|  * CIO15     P20         KBC P21 fucntion
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|  * CIO16     I2C_CLK     I2C Clock
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|  * CIO17     I2C_DAT     I2C Data
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|  *
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|  * CIO20     -
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|  * CIO21     -
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|  * CIO22     -
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|  * CIO23     -
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|  * CIO24     -
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|  * CIO25     LOCK        Keylock
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|  *
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|  * CIO30     KBC_CLK     Keybaord Clock
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|  * CIO31     CS0J        General Chip Select decoder CS0J
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|  * CIO32     CS1J        General Chip Select decoder CS1J
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|  * CIO33     ALT_KCLK    Alternative Keyboard Clock
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|  * CIO34     ALT_KDAT    Alternative Keyboard Data
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|  * CIO35     ALT_MCLK    Alternative Mouse Clock
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|  * CIO36     ALT_MDAT    Alternative Mouse Data
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|  * CIO37     ALT_KBC     Alternative KBC select
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|  *
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|  * The CIO use an indirect address scheme.
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|  *
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|  * Reigster 3 in the SIO is used to select the index and data
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|  * port addresses where the CIO I/O registers show up.
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|  * The function selection registers are accessible under
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|  * function SIO 8.
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|  *
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|  * SIO reigster 3 (CIO Address Selection) bit definitions:
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|  * bit 7   CIO index and data registers enabled
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|  * bit 1-0 CIO indirect registers port address select
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|  *	 0  index = 0xE0 data = 0xE1
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|  *       1  index = 0xE2 data = 0xE3
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|  *       2  index = 0xE4 data = 0xE5
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|  *       3  index = 0xEA data = 0xEB
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|  *
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|  * There are three CIO I/O register accessed via CIO index port and CIO data port
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|  * 0x01     CIO 10-17 data
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|  * 0x02     CIO 20-25 data (bits 7-6 unused)
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|  * 0x03     CIO 30-37 data
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|  *
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|  *
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|  * The pin function is accessed through normal
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|  * SIO registers, each register have the same format:
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|  *
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|  * Bit   Function                     Value
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|  * 0     Input/output                 1=input
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|  * 1     Polarity of signal           1=inverted
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|  * 2     Unused                       ??
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|  * 3     Function (normal or special) 1=special
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|  * 7-4   Unused
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|  *
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|  * SIO REG
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|  * 0xe0     CIO 10 Config
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|  * 0xe1     CIO 11 Config
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|  * 0xe2     CIO 12 Config
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|  * 0xe3     CIO 13 Config
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|  * 0xe4     CIO 14 Config
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|  * 0xe5     CIO 15 Config
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|  * 0xe6     CIO 16 Config
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|  * 0xe7     CIO 16 Config
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|  *
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|  * 0xe8     CIO 20 Config
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|  * 0xe9     CIO 21 Config
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|  * 0xea     CIO 22 Config
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|  * 0xeb     CIO 23 Config
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|  * 0xec     CIO 24 Config
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|  * 0xed     CIO 25 Config
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|  *
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|  * 0xf5     CIO 30 Config
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|  * 0xf6     CIO 31 Config
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|  * 0xf7     CIO 32 Config
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|  * 0xf8     CIO 33 Config
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|  * 0xf9     CIO 34 Config
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|  * 0xfa     CIO 35 Config
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|  * 0xfb     CIO 36 Config
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|  * 0xfc     CIO 37 Config
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|  *
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|  */
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| 
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| #define ALI_CIO_PORT_SEL 0x83
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| #define ALI_CIO_INDEX    0xea
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| #define ALI_CIO_DATA     0xeb
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| 
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| void ali512x_set_cio(int enabled)
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| {
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| 	int i;
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| 
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| 	ALI_OPEN();
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| 
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| 	if (enabled) {
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| 		ali_write(0x3, ALI_CIO_PORT_SEL);    /* Enable CIO data register */
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| 	} else {
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| 		ali_write(0x3, ALI_CIO_PORT_SEL & ~0x80);
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| 	}
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| 
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| 	ALI_SELDEV(8);
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| 
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| 	ali_write(0x30, enabled?1:0);
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| 
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| 	/* set all pins to input to start with */
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| 	for (i=0xe0;i<0xee;i++) {
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| 		ali_write(i, 1);
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| 	}
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| 
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| 	for (i=0xf5;i<0xfe;i++) {
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| 		ali_write(i, 1);
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| 	}
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| 
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| 	ALI_CLOSE();
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| }
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| 
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| 
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| void ali512x_cio_function(int pin, int special, int inv, int input)
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| {
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| 	u8 data;
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| 	u8 addr;
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| 
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| 	/* valid pins are 10-17, 20-25 and 30-37 */
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| 	if (pin >= 10 && pin <= 17) {
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| 		addr = 0xe0+(pin&7);
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| 	} else if (pin >= 20 && pin <= 25) {
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| 		addr = 0xe8+(pin&7);
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| 	} else if (pin >= 30 && pin <= 37) {
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| 		addr = 0xf5+(pin&7);
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| 	} else {
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| 		return;
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| 	}
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| 
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| 	ALI_OPEN();
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| 
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| 	ALI_SELDEV(8);
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| 
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| 
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| 	data=0xf4;
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| 	if (special) {
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| 		data |= 0x08;
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| 	} else {
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| 		if (inv) {
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| 			data |= 0x02;
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| 		}
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| 		if (input) {
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| 			data |= 0x01;
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| 		}
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| 	}
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| 
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| 	ali_write(addr, data);
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| 
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| 	ALI_CLOSE();
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| }
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| 
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| void ali512x_cio_out(int pin, int value)
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| {
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| 	u8 reg;
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| 	u8 data;
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| 	u8 bit;
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| 
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| 	reg = pin/10;
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| 	bit = 1 << (pin%10);
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| 
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| 
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| 	outb(reg, ALI_CIO_INDEX);     /* select I/O register */
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| 	data = inb(ALI_CIO_DATA);
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| 	if (value) {
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| 		data |= bit;
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| 	} else {
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| 		data &= ~bit;
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| 	}
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| 	outb(data, ALI_CIO_DATA);
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| }
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| 
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| int ali512x_cio_in(int pin)
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| {
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| 	u8 reg;
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| 	u8 data;
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| 	u8 bit;
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| 
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| 	/* valid pins are 10-17, 20-25 and 30-37 */
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| 	reg = pin/10;
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| 	bit = 1 << (pin%10);
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| 
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| 
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| 	outb(reg, ALI_CIO_INDEX);     /* select I/O register */
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| 	data = inb(ALI_CIO_DATA);
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| 
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| 	return data & bit;
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| }
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