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https://xff.cz/git/u-boot/
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a6e50a88d8
This enables the necessary clocks, in AHB0 and in PLL6_CFG. This is done for sun7i only since I don't have access to any other sunxi platforms with sata included. The PHY setup is derived from the Alwinner releases and Linux, but is mostly undocumented. The Allwinner AHCI controller also requires some magic (and, again, undocumented) DMA initialisation when starting a port. This is added under a suitable ifdef. This option is enabled for Cubieboard, Cubieboard2 and Cubietruck based on contents of Linux DTS files, including SATA power pin config taken from the DTS. All build tested, but runtime tested on Cubieboard2 and Cubietruck only. Signed-off-by: Ian Campbell <ijc@hellion.org.uk> Acked-by: Hans de Goede <hdegoede@redhat.com> Signed-off-by: Hans de Goede <hdegoede@redhat.com>
232 lines
6.1 KiB
C
232 lines
6.1 KiB
C
/*
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* (C) Copyright 2012-2012 Henrik Nordstrom <henrik@henriknordstrom.net>
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*
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* (C) Copyright 2007-2011
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* Allwinner Technology Co., Ltd. <www.allwinnertech.com>
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* Tom Cubie <tangliang@allwinnertech.com>
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*
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* Configuration settings for the Allwinner sunxi series of boards.
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*
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* SPDX-License-Identifier: GPL-2.0+
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*/
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#ifndef _SUNXI_COMMON_CONFIG_H
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#define _SUNXI_COMMON_CONFIG_H
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/*
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* High Level Configuration Options
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*/
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#define CONFIG_SUNXI /* sunxi family */
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#ifdef CONFIG_SPL_BUILD
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#ifndef CONFIG_SPL_FEL
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#define CONFIG_SYS_THUMB_BUILD /* Thumbs mode to save space in SPL */
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#endif
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#endif
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#include <asm/arch/cpu.h> /* get chip and board defs */
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#define CONFIG_SYS_TEXT_BASE 0x4a000000
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/*
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* Display CPU information
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*/
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#define CONFIG_DISPLAY_CPUINFO
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/* Serial & console */
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#define CONFIG_SYS_NS16550
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#define CONFIG_SYS_NS16550_SERIAL
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/* ns16550 reg in the low bits of cpu reg */
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#define CONFIG_SYS_NS16550_REG_SIZE -4
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#define CONFIG_SYS_NS16550_CLK 24000000
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#define CONFIG_SYS_NS16550_COM1 SUNXI_UART0_BASE
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#define CONFIG_SYS_NS16550_COM2 SUNXI_UART1_BASE
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#define CONFIG_SYS_NS16550_COM3 SUNXI_UART2_BASE
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#define CONFIG_SYS_NS16550_COM4 SUNXI_UART3_BASE
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/* DRAM Base */
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#define CONFIG_SYS_SDRAM_BASE 0x40000000
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#define CONFIG_SYS_INIT_RAM_ADDR 0x0
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#define CONFIG_SYS_INIT_RAM_SIZE 0x8000 /* 32 KiB */
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#define CONFIG_SYS_INIT_SP_OFFSET \
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(CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
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#define CONFIG_SYS_INIT_SP_ADDR \
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(CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_SP_OFFSET)
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#define CONFIG_NR_DRAM_BANKS 1
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#define PHYS_SDRAM_0 CONFIG_SYS_SDRAM_BASE
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#define PHYS_SDRAM_0_SIZE 0x80000000 /* 2 GiB */
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#ifdef CONFIG_AHCI
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#define CONFIG_LIBATA
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#define CONFIG_SCSI_AHCI
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#define CONFIG_SCSI_AHCI_PLAT
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#define CONFIG_SUNXI_AHCI
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#define CONFIG_SYS_SCSI_MAX_SCSI_ID 1
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#define CONFIG_SYS_SCSI_MAX_LUN 1
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#define CONFIG_SYS_SCSI_MAX_DEVICE (CONFIG_SYS_SCSI_MAX_SCSI_ID * \
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CONFIG_SYS_SCSI_MAX_LUN)
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#define CONFIG_CMD_SCSI
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#endif
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#define CONFIG_CMD_MEMORY
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#define CONFIG_CMD_SETEXPR
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#define CONFIG_SETUP_MEMORY_TAGS
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#define CONFIG_CMDLINE_TAG
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#define CONFIG_INITRD_TAG
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/* mmc config */
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#define CONFIG_MMC
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#define CONFIG_GENERIC_MMC
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#define CONFIG_CMD_MMC
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#define CONFIG_MMC_SUNXI
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#define CONFIG_MMC_SUNXI_SLOT 0
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#define CONFIG_ENV_IS_IN_MMC
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#define CONFIG_SYS_MMC_ENV_DEV 0 /* first detected MMC controller */
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/* 4MB of malloc() pool */
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#define CONFIG_SYS_MALLOC_LEN (CONFIG_ENV_SIZE + (4 << 20))
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/*
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* Miscellaneous configurable options
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*/
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#define CONFIG_CMD_ECHO
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#define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */
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#define CONFIG_SYS_PBSIZE 384 /* Print Buffer Size */
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#define CONFIG_SYS_MAXARGS 16 /* max number of command args */
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#define CONFIG_SYS_GENERIC_BOARD
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/* Boot Argument Buffer Size */
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#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE
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#define CONFIG_SYS_LOAD_ADDR 0x48000000 /* default load address */
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/* standalone support */
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#define CONFIG_STANDALONE_LOAD_ADDR 0x48000000
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#define CONFIG_SYS_HZ 1000
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/* baudrate */
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#define CONFIG_BAUDRATE 115200
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/* The stack sizes are set up in start.S using the settings below */
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#define CONFIG_STACKSIZE (256 << 10) /* 256 KiB */
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/* FLASH and environment organization */
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#define CONFIG_SYS_NO_FLASH
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#define CONFIG_SYS_MONITOR_LEN (512 << 10) /* 512 KiB */
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#define CONFIG_IDENT_STRING " Allwinner Technology"
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#define CONFIG_ENV_OFFSET (544 << 10) /* (8 + 24 + 512) KiB */
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#define CONFIG_ENV_SIZE (128 << 10) /* 128 KiB */
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#define CONFIG_EXTRA_ENV_SETTINGS \
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"bootm_size=0x10000000\0"
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#define CONFIG_SYS_BOOT_GET_CMDLINE
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#include <config_cmd_default.h>
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#define CONFIG_FAT_WRITE /* enable write access */
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#define CONFIG_SPL_FRAMEWORK
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#define CONFIG_SPL_LIBCOMMON_SUPPORT
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#define CONFIG_SPL_SERIAL_SUPPORT
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#define CONFIG_SPL_LIBGENERIC_SUPPORT
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#ifdef CONFIG_SPL_FEL
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#define CONFIG_SPL_LDSCRIPT "arch/arm/cpu/armv7/sunxi/u-boot-spl-fel.lds"
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#define CONFIG_SPL_START_S_PATH "arch/arm/cpu/armv7/sunxi"
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#define CONFIG_SPL_TEXT_BASE 0x2000
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#define CONFIG_SPL_MAX_SIZE 0x4000 /* 16 KiB */
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#else /* CONFIG_SPL */
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#define CONFIG_SPL_BSS_START_ADDR 0x4ff80000
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#define CONFIG_SPL_BSS_MAX_SIZE 0x80000 /* 512 KiB */
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#define CONFIG_SPL_TEXT_BASE 0x20 /* sram start+header */
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#define CONFIG_SPL_MAX_SIZE 0x5fe0 /* 24KB on sun4i/sun7i */
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#define CONFIG_SPL_LIBDISK_SUPPORT
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#define CONFIG_SPL_MMC_SUPPORT
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#define CONFIG_SPL_LDSCRIPT "arch/arm/cpu/armv7/sunxi/u-boot-spl.lds"
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#define CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR 80 /* 40KiB */
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#define CONFIG_SPL_PAD_TO 32768 /* decimal for 'dd' */
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#endif /* CONFIG_SPL */
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/* end of 32 KiB in sram */
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#define LOW_LEVEL_SRAM_STACK 0x00008000 /* End of sram */
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#define CONFIG_SPL_STACK LOW_LEVEL_SRAM_STACK
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#define CONFIG_SYS_SPL_MALLOC_START 0x4ff00000
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#define CONFIG_SYS_SPL_MALLOC_SIZE 0x00080000 /* 512 KiB */
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#undef CONFIG_CMD_FPGA
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#undef CONFIG_CMD_NET
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#undef CONFIG_CMD_NFS
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/* I2C */
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#define CONFIG_SPL_I2C_SUPPORT
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#define CONFIG_SYS_I2C
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#define CONFIG_SYS_I2C_MVTWSI
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#define CONFIG_SYS_I2C_SPEED 400000
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#define CONFIG_SYS_I2C_SLAVE 0x7f
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#define CONFIG_CMD_I2C
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/* PMU */
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#if defined CONFIG_AXP152_POWER || defined CONFIG_AXP209_POWER || defined CONFIG_AXP221_POWER
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#define CONFIG_SPL_POWER_SUPPORT
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#endif
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#ifndef CONFIG_CONS_INDEX
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#define CONFIG_CONS_INDEX 1 /* UART0 */
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#endif
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/* GPIO */
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#define CONFIG_SUNXI_GPIO
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#define CONFIG_CMD_GPIO
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/* Ethernet support */
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#ifdef CONFIG_SUNXI_EMAC
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#define CONFIG_MII /* MII PHY management */
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#endif
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#ifdef CONFIG_SUNXI_GMAC
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#define CONFIG_DESIGNWARE_ETH /* GMAC can use designware driver */
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#define CONFIG_DW_AUTONEG
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#define CONFIG_PHY_GIGE /* GMAC can use gigabit PHY */
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#define CONFIG_PHY_ADDR 1
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#define CONFIG_MII /* MII PHY management */
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#define CONFIG_PHYLIB
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#endif
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#ifdef CONFIG_CMD_NET
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#define CONFIG_CMD_NFS
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#define CONFIG_CMD_DNS
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#define CONFIG_NETCONSOLE
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#define CONFIG_BOOTP_DNS2
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#define CONFIG_BOOTP_SEND_HOSTNAME
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#endif
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#if !defined CONFIG_ENV_IS_IN_MMC && \
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!defined CONFIG_ENV_IS_IN_NAND && \
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!defined CONFIG_ENV_IS_IN_FAT && \
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!defined CONFIG_ENV_IS_IN_SPI_FLASH
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#define CONFIG_ENV_IS_NOWHERE
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#endif
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#define CONFIG_MISC_INIT_R
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#ifndef CONFIG_SPL_BUILD
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#include <config_distro_defaults.h>
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#endif
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#endif /* _SUNXI_COMMON_CONFIG_H */
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