mirror of
https://xff.cz/git/u-boot/
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148447d288
The GPIO3 has to be available early during U-Boot proper start up for DRAM size detect to work correctly. The GPIO3 is currently available in SPL and late in U-Boot proper, which is insufficient. Add the missing bootph-all to make the GPIO3 available also early in U-Boot proper. Signed-off-by: Marek Vasut <marex@denx.de>
208 lines
3.1 KiB
Plaintext
208 lines
3.1 KiB
Plaintext
// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
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/*
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* Copyright (C) 2022 Marek Vasut <marex@denx.de>
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*/
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#include "imx8mp-u-boot.dtsi"
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/ {
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aliases {
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eeprom0 = &eeprom0;
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eeprom1 = &eeprom1;
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mmc0 = &usdhc2; /* MicroSD */
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mmc1 = &usdhc3; /* eMMC */
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mmc2 = &usdhc1; /* SDIO */
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};
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config {
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dh,ram-coding-gpios = <&gpio3 22 0>, <&gpio3 23 0>, <&gpio3 24 0>;
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};
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wdt-reboot {
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compatible = "wdt-reboot";
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wdt = <&wdog1>;
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bootph-pre-ram;
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};
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};
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&buck4 {
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bootph-pre-ram;
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};
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&buck5 {
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bootph-pre-ram;
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};
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&gpio1 {
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bootph-pre-ram;
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};
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&gpio2 {
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bootph-pre-ram;
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};
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&gpio3 {
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bootph-all;
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bootph-pre-ram;
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};
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&gpio4 {
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bootph-pre-ram;
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};
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&gpio5 {
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bootph-pre-ram;
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};
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&i2c3 {
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bootph-pre-ram;
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};
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&pinctrl_i2c3 {
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bootph-pre-ram;
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};
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&pinctrl_i2c3_gpio {
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bootph-pre-ram;
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};
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&pinctrl_pmic {
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bootph-pre-ram;
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};
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&pinctrl_uart1 {
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bootph-pre-ram;
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};
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&pinctrl_usdhc2 {
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bootph-pre-ram;
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};
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&pinctrl_usdhc2_100mhz {
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bootph-pre-ram;
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};
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&pinctrl_usdhc2_200mhz {
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bootph-pre-ram;
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};
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&pinctrl_usdhc2_vmmc {
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bootph-pre-ram;
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};
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&pinctrl_usdhc3 {
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bootph-pre-ram;
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};
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&pinctrl_usdhc3_100mhz {
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bootph-pre-ram;
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};
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&pinctrl_usdhc3_100mhz {
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bootph-pre-ram;
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};
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&pmic {
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bootph-pre-ram;
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regulators {
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bootph-pre-ram;
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};
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};
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®_usdhc2_vmmc {
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bootph-pre-ram;
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};
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&uart1 {
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bootph-pre-ram;
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};
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/* SDIO WiFi */
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&usdhc1 {
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status = "disabled";
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};
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&usdhc2 {
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bootph-pre-ram;
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};
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&usdhc3 {
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bootph-pre-ram;
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};
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&wdog1 {
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bootph-pre-ram;
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};
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&binman {
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itb {
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fit {
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images {
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fdt-dto-imx8mp-dhcom-som-overlay-eth1xfast {
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description = "imx8mp-dhcom-som-overlay-eth1xfast";
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type = "flat_dt";
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compression = "none";
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blob-ext {
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filename = "imx8mp-dhcom-som-overlay-eth1xfast.dtbo";
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};
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};
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fdt-dto-imx8mp-dhcom-som-overlay-eth2xfast {
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description = "imx8mp-dhcom-som-overlay-eth2xfast";
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type = "flat_dt";
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compression = "none";
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blob-ext {
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filename = "imx8mp-dhcom-som-overlay-eth2xfast.dtbo";
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};
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};
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fdt-dto-imx8mp-dhcom-pdk-overlay-eth2xfast {
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description = "imx8mp-dhcom-pdk-overlay-eth2xfast";
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type = "flat_dt";
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compression = "none";
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blob-ext {
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filename = "imx8mp-dhcom-pdk-overlay-eth2xfast.dtbo";
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};
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};
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fdt-dto-imx8mp-dhcom-som-overlay-rev100 {
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description = "imx8mp-dhcom-som-overlay-rev100";
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type = "flat_dt";
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compression = "none";
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blob-ext {
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filename = "imx8mp-dhcom-som-overlay-rev100.dtbo";
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};
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};
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fdt-dto-imx8mp-dhcom-pdk3-overlay-rev100 {
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description = "imx8mp-dhcom-pdk3-overlay-rev100";
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type = "flat_dt";
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compression = "none";
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blob-ext {
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filename = "imx8mp-dhcom-pdk3-overlay-rev100.dtbo";
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};
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};
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};
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configurations {
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default = "@config-DEFAULT-SEQ";
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@config-SEQ {
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fdt = "fdt-1",
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"fdt-dto-imx8mp-dhcom-som-overlay-eth1xfast",
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"fdt-dto-imx8mp-dhcom-som-overlay-eth2xfast",
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"fdt-dto-imx8mp-dhcom-pdk-overlay-eth2xfast",
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"fdt-dto-imx8mp-dhcom-som-overlay-rev100",
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"fdt-dto-imx8mp-dhcom-pdk3-overlay-rev100";
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};
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};
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};
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};
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};
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