mirror of
https://xff.cz/git/u-boot/
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c316ee674f
Xilinx changes for v2022.10 cpu: - Add driver for microblaze cpu net: - Add support for DM_ETH_PHY to AXI emac and emaclite xilinx: - Switch platforms to DM_ETH_PHY - DT chagnes in ZynqMP and Zynq - Enable support for SquashFS zynqmp: - Add support for KR260 boards - Move BSS from address 0 - Move platform identification from board code to soc driver - Improve zynqmp_psu_init_minimize versal: - Enable loading app at EL1 serial: - Setup default address and clock rates for DEBUG uarts pinctrl: - Add support for tri state and output enable properties relocate-rela: - Clean relocate-rela implementation for ARM64 - Add support for Microblaze microblaze: - Add support for runtime relocation - Rework cache handling (wiring, Kconfig) based on cpuinfo - Remove interrupt support timer: - Extract axi timer driver from Microblaze to generic location
75 lines
982 B
Plaintext
75 lines
982 B
Plaintext
/* SPDX-License-Identifier: GPL-2.0+ */
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/*
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* (C) Copyright 2004 Atmark Techno, Inc.
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*
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* Yasushi SHOJI <yashi@atmark-techno.com>
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*/
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OUTPUT_ARCH(microblaze)
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ENTRY(_start)
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SECTIONS
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{
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.text ALIGN(0x4):
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{
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__text_start = .;
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arch/microblaze/cpu/start.o (.text)
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*(.text*)
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__text_end = .;
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}
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.rodata ALIGN(0x4):
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{
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__rodata_start = .;
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*(SORT_BY_ALIGNMENT(SORT_BY_NAME(.rodata*)))
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__rodata_end = .;
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}
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.data ALIGN(0x4):
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{
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__data_start = .;
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*(.data*)
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__data_end = .;
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}
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.got ALIGN(4):
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{
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_got_start = .;
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*(.got*)
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. = ALIGN(4);
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_got_end = .;
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}
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. = ALIGN(4);
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__u_boot_list : {
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KEEP(*(SORT(__u_boot_list*)));
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}
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__init_end = . ;
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. = ALIGN(4);
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__rel_dyn_start = .;
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.rela.dyn : {
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*(.rela.dyn)
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}
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__rel_dyn_end = .;
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. = ALIGN(4);
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__dyn_sym_start = .;
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.dynsym : {
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*(.dynsym)
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}
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__dyn_sym_end = .;
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.bss ALIGN(0x4):
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{
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__bss_start = .;
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*(.sbss)
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*(.scommon)
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*(.bss*)
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*(COMMON)
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. = ALIGN(4);
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__bss_end = .;
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}
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_end = . ;
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}
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