Patrice Chotard 990dba6498 clk: clk_stm32f: Fix PLLSAICFGR_PLLSAIP_4 divider value ...

PLLSAIP divider uses 2 bits (bits 16 and 17) into RCC_PLLSAICFGR
register, available combination are :
  00: PLLSAIP = 2
  01: PLLSAIP = 4
  10: PLLSAIP = 6
  11: PLLSAIP = 8

Previously, the divider value was incorrectly set to 6.

Signed-off-by: Patrice Chotard <patrice.chotard@st.com>

2018-01-28 09:39:15 -05:00

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aspeed

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at91

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2017-11-29 22:30:50 -05:00

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Merge branch 'rmobile-mx' of git://git.denx.de/u-boot-sh

2018-01-27 18:25:00 -05:00

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tegra

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uniphier

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2017-10-15 22:32:25 +09:00

clk_bcm6345.c

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clk_boston.c

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clk_fixed_rate.c

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2018-01-21 10:01:02 -07:00

clk_pic32.c

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2018-01-24 12:03:43 +05:30

clk_sandbox_test.c

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clk_sandbox.c

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clk_stm32f.c

clk: clk_stm32f: Fix PLLSAICFGR_PLLSAIP_4 divider value

2018-01-28 09:39:15 -05:00

clk_stm32h7.c

stm32: fix STMicroelectronics copyright

2017-11-06 09:51:01 -05:00

clk_zynq.c

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clk_zynqmp.c

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clk-hsdk-cgu.c

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2018-01-19 17:59:35 +03:00

clk-uclass.c

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Kconfig

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Makefile

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2018-01-21 10:01:02 -07:00