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	There is no Kconfig option for this code, but it seems to be useful. Add one. Signed-off-by: Simon Glass <sjg@chromium.org>
		
			
				
	
	
		
			174 lines
		
	
	
		
			4.9 KiB
		
	
	
	
		
			Plaintext
		
	
	
	
	
	
			
		
		
	
	
			174 lines
		
	
	
		
			4.9 KiB
		
	
	
	
		
			Plaintext
		
	
	
	
	
	
| menu "FPGA support"
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| 
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| config FPGA
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| 	bool
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| 
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| config FPGA_ALTERA
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| 	bool "Enable Altera FPGA drivers"
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| 	select FPGA
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| 	help
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| 	  Say Y here to enable the Altera FPGA driver
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| 
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| 	  This provides basic infrastructure to support Altera FPGA devices.
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| 	  Enable Altera FPGA specific functions which includes bitstream
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| 	  (in BIT format), fpga and device validation.
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| 
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| config FPGA_SOCFPGA
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| 	bool "Enable Gen5 and Arria10 common FPGA drivers"
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| 	select FPGA_ALTERA
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| 	help
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| 	  Say Y here to enable the Gen5 and Arria10 common FPGA driver
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| 
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| 	  This provides common functionality for Gen5 and Arria10 devices.
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| 
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| config FPGA_STRATIX_II
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| 	bool "Enable Stratix II FPGA drivers"
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| 	depends on FPGA_ALTERA
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| 	help
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| 	  Say Y here to enable the Altera Stratix II FPGA-specific driver.
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| 
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| config FPGA_STRATIX_V
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| 	bool "Enable Stratix V FPGA drivers"
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| 	depends on FPGA_ALTERA
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| 	help
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| 	  Say Y here to enable the Altera Stratix V FPGA specific driver.
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| 
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| config FPGA_ACEX1K
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| 	bool "Enable Altera ACEX 1K driver"
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| 	depends on FPGA_ALTERA
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| 	help
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| 	  Say Y here to enable the Altera ACEX 1K FPGA specific driver.
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| 
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| config FPGA_CYCLON2
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| 	bool "Enable Altera FPGA driver for Cyclone II"
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| 	depends on FPGA_ALTERA
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| 	help
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| 	  Say Y here to enable the Altera Cyclone II FPGA specific driver
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| 
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| 	  This provides common functionality for Altera Cyclone II devices.
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| 	  Enable FPGA driver for loading bitstream in BIT and BIN format
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| 	  on Altera Cyclone II device.
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| 
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| config FPGA_INTEL_SDM_MAILBOX
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| 	bool "Enable Intel FPGA Full Reconfiguration SDM Mailbox driver"
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| 	depends on TARGET_SOCFPGA_SOC64
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| 	select FPGA_ALTERA
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| 	help
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| 	  Say Y here to enable the Intel FPGA Full Reconfig SDM Mailbox driver
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| 
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| 	  This provides common functionality for Intel FPGA devices.
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| 	  Enable FPGA driver for writing full bitstream into Intel FPGA
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| 	  devices through SDM (Secure Device Manager) Mailbox.
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| 
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| config FPGA_LATTICE
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| 	bool "Enable Lattice FPGA driver"
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| 	help
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| 	  This is used for the lattice FPGAs. Please check the source code as
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| 	  there is no documentation for this at present.
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| 
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| config FPGA_XILINX
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| 	bool "Enable Xilinx FPGA drivers"
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| 	select FPGA
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| 	help
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| 	  Enable Xilinx FPGA specific functions which includes bitstream
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| 	  (in BIT format), fpga and device validation.
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| 
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| config FPGA_ZYNQMPPL
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| 	bool "Enable Xilinx FPGA driver for ZynqMP"
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| 	depends on FPGA_XILINX
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| 	help
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| 	  Enable FPGA driver for loading bitstream in BIT and BIN format
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| 	  on Xilinx Zynq UltraScale+ (ZynqMP) device.
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| 
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| config FPGA_VERSALPL
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| 	bool "Enable Xilinx FPGA driver for Versal"
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| 	depends on FPGA_XILINX
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| 	help
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| 	  Enable FPGA driver for loading bitstream in PDI format on Xilinx
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| 	  Versal device. PDI is a new programmable device image format for
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| 	  Versal. The bitstream will only be generated as PDI for Versal
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| 	  platform.
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| 
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| config FPGA_SPARTAN2
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| 	bool "Enable Spartan2 FPGA driver"
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| 	depends on FPGA_XILINX
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| 	help
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| 	  Enable Spartan2 FPGA driver.
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| 
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| config FPGA_SPARTAN3
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| 	bool "Enable Spartan3 FPGA driver"
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| 	depends on FPGA_XILINX
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| 	help
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| 	  Enable Spartan3 FPGA driver for loading in BIT format.
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| 
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| config FPGA_VIRTEX2
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| 	bool "Enable Xilinx Virtex-II and later FPGA driver"
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| 	depends on FPGA_XILINX
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| 	help
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| 	  Enable Virtex-II FPGA driver for loading in BIT format. This driver
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| 	  also supports many newer Xilinx FPGA families.
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| 
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| config SYS_FPGA_CHECK_BUSY
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| 	bool "Perform busy check during load from FPGA"
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| 	depends on FPGA_SPARTAN2 || FPGA_SPARTAN3 || FPGA_VIRTEX2
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| 
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| config FPGA_ZYNQPL
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| 	bool "Enable Xilinx FPGA for Zynq"
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| 	depends on ARCH_ZYNQ
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| 	help
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| 	  Enable FPGA driver for loading bitstream in BIT and BIN format
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| 	  on Xilinx Zynq devices.
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| 
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| config SYS_FPGA_CHECK_CTRLC
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| 	bool "Allow Control-C to interrupt FPGA configuration"
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| 	depends on FPGA
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| 	help
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| 	  User can interrupt FPGA configuration by pressing CTRL+C.
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| 
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| config SYS_FPGA_PROG_FEEDBACK
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| 	bool "Progress output during FPGA configuration"
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| 	depends on FPGA
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| 	default y if FPGA_VIRTEX2
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| 	help
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| 	  Enable printing of hash marks during FPGA configuration.
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| 
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| config FPGA_LOAD_SECURE
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| 	bool "Enable loading secure bitstreams"
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| 	depends on FPGA
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| 	help
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| 	  Enables the fpga loads() functions that are used to load secure
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| 	  (authenticated or encrypted or both) bitstreams on to FPGA.
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| 
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| config SPL_FPGA_LOAD_SECURE
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| 	bool "Enable loading secure bitstreams for SPL"
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| 	depends on SPL_FPGA
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| 	help
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| 	  Enables the fpga loads() functions that are used to load secure
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| 	  (authenticated or encrypted or both) bitstreams on to FPGA.
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| 
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| config DM_FPGA
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| 	bool "Enable Driver Model for FPGA drivers"
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| 	depends on DM
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| 	select FPGA
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| 	help
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| 	  Enable driver model for Field-Programmable Gate Array (FPGA) devices.
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| 	  The devices cover a wide range of applications and are configured at
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| 	  runtime by loading a bitstream into the FPGA device.
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| 	  Loading a bitstream from any kind of storage is the main task of the
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| 	  FPGA drivers.
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| 	  For now this uclass has no methods yet.
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| 
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| config SANDBOX_FPGA
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| 	bool "Enable sandbox FPGA driver"
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| 	depends on SANDBOX && DM_FPGA
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| 	help
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| 	  This is a driver model based FPGA driver for sandbox.
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| 	  Currently it is a stub only, as there are no usable uclass methods yet.
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| 
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| config MAX_FPGA_DEVICES
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| 	int "Maximum number of FPGA devices"
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| 	depends on FPGA
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| 	default 5
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| 
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| endmenu
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