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2d67a095dc
Driver for Cadence EDAC DDR controller, as found in the Renesas RZ/N1. Signed-off-by: Ralph Siemsen <ralph.siemsen@linaro.org> Reviewed-by: Marek Vasut <marek.vasut+renesas@mailbox.org>
176 lines
6.3 KiB
C
176 lines
6.3 KiB
C
/* SPDX-License-Identifier: BSD-2-Clause */
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/*
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* Cadence DDR Controller
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*
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* Copyright (C) 2015 Renesas Electronics Europe Ltd
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*/
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#ifndef CADENCE_DDR_CTRL_H
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#define CADENCE_DDR_CTRL_H
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enum cdns_ddr_range_prot {
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CDNS_DDR_RANGE_PROT_BITS_PRIV_SECURE = 0,
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CDNS_DDR_RANGE_PROT_BITS_SECURE = 1,
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CDNS_DDR_RANGE_PROT_BITS_PRIV = 2,
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CDNS_DDR_RANGE_PROT_BITS_FULL = 3,
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};
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/**
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* Initialise the Cadence DDR Controller, but doesn't start it.
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*
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* It sets up the controller so that all 4 AXI slave ports allow access to all
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* of the DDR with the same settings. This means that:
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* - Full access permisions.
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* - All read/write priorities are set to 2.
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* - Bandwidth is set to 50%, overflow is allowed, i.e. it's a soft limit.
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* If you want different properties for different ports and/or addr ranges, call
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* the other functions before calling cdns_ddr_ctrl_start().
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*
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* @ddr_ctrl_base Physical address of the DDR Controller.
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* @async 0 if DDR clock is synchronous with the controller clock
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* otherwise 1.
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* @reg0 Pointer to array of 32-bit values to be written to registers
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* 0 to 87. The values are generated by Cadence TCL scripts.
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* @reg350 Pointer to array of 32-bit values to be written to registers
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* 350 to 374. The values are generated by Cadence TCL scripts.
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* @ddr_start_addr Physical address of the start of DDR.
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* @ddr_size Size of the DDR in bytes. The controller will set the port
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* protection range to match this size.
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* @enable_ecc 0 to disable ECC, 1 to enable it.
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* @enable_8bit 0 to use 16-bit bus width, 1 to use 8-bit bus width.
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*/
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void cdns_ddr_ctrl_init(void *ddr_ctrl_base, int async,
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const u32 *reg0, const u32 *reg350,
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u32 ddr_start_addr, u32 ddr_size,
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int enable_ecc, int enable_8bit);
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/**
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* Start the Cadence DDR Controller.
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*
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* @ddr_ctrl_base Physical address of the DDR Controller.
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*/
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void cdns_ddr_ctrl_start(void *ddr_ctrl_base);
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/**
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* Set the priority for read and write operations for a specific AXI slave port.
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*
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* @base Physical address of the DDR Controller.
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* @port Port number. Range is 0 to 3.
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* @read_pri Priority for reads. Range is 0 to 3, where 0 is highest priority.
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* @write_pri Priority for writes. Range is 0 to 3, where 0 is highest priority.
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*/
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void cdns_ddr_set_port_rw_priority(void *base, int port,
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u8 read_pri, u8 write_pri);
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/**
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* Specify address range for a protection entry, for a specific AXI slave port.
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*
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* @base Physical address of the DDR Controller.
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* @port Port number. Range is 0 to 3.
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* @entry The protection entry. Range is 0 to 15.
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* @start_addr Physical of the address range, must be aligned to 16KB.
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* @size Size of the address range, must be multiple of 16KB.
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*/
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void cdns_ddr_enable_port_addr_range(void *base, int port, int entry,
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u32 addr_start, u32 size);
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/**
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* Specify address range for a protection entry, for all AXI slave ports.
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*
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* @base Physical address of the DDR Controller.
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* @entry The protection entry. Range is 0 to 15.
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* @start_addr Physical of the address range, must be aligned to 16KB.
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* @size Size of the address range, must be multiple of 16KB.
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*/
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void cdns_ddr_enable_addr_range(void *base, int entry,
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u32 addr_start, u32 size);
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/**
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* Specify protection entry details, for a specific AXI slave port.
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*
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* See the hardware manual for details of the range check bits.
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*
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* @base Physical address of the DDR Controller.
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* @port Port number. Range is 0 to 3.
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* @entry The protection entry. Range is 0 to 15.
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*/
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void cdns_ddr_enable_port_prot(void *base, int port, int entry,
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enum cdns_ddr_range_prot range_protection_bits,
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u16 range_RID_check_bits,
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u16 range_WID_check_bits,
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u8 range_RID_check_bits_ID_lookup,
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u8 range_WID_check_bits_ID_lookup);
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/**
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* Specify protection entry details, for all AXI slave ports.
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*
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* See the hardware manual for details of the range check bits.
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*
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* @base Physical address of the DDR Controller.
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* @entry The protection entry. Range is 0 to 15.
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*/
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void cdns_ddr_enable_prot(void *base, int entry,
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enum cdns_ddr_range_prot range_protection_bits,
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u16 range_RID_check_bits,
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u16 range_WID_check_bits,
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u8 range_RID_check_bits_ID_lookup,
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u8 range_WID_check_bits_ID_lookup);
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/**
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* Specify bandwidth for each AXI port.
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*
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* See the hardware manual for details of the range check bits.
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*
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* @base Physical address of the DDR Controller.
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* @port Port number. Range is 0 to 3.
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* @max_percent 0 to 100.
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*/
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void cdns_ddr_set_port_bandwidth(void *base, int port,
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u8 max_percent, u8 overflow_ok);
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/* Standard JEDEC registers */
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#define MODE_REGISTER_MASK (3 << 14)
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#define MODE_REGISTER_MR0 (0 << 14)
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#define MODE_REGISTER_MR1 (1 << 14)
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#define MODE_REGISTER_MR2 (2 << 14)
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#define MODE_REGISTER_MR3 (3 << 14)
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#define MR1_DRIVE_STRENGTH_MASK ((1 << 5) | (1 << 1))
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#define MR1_DRIVE_STRENGTH_34_OHMS ((0 << 5) | (1 << 1))
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#define MR1_DRIVE_STRENGTH_40_OHMS ((0 << 5) | (0 << 1))
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#define MR1_ODT_IMPEDANCE_MASK ((1 << 9) | (1 << 6) | (1 << 2))
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#define MR1_ODT_IMPEDANCE_60_OHMS ((0 << 9) | (0 << 6) | (1 << 2))
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#define MR1_ODT_IMPEDANCE_120_OHMS ((0 << 9) | (1 << 6) | (0 << 2))
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#define MR1_ODT_IMPEDANCE_40_OHMS ((0 << 9) | (1 << 6) | (1 << 2))
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#define MR1_ODT_IMPEDANCE_20_OHMS ((1 << 9) | (0 << 6) | (0 << 2))
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#define MR1_ODT_IMPEDANCE_30_OHMS ((1 << 9) | (0 << 6) | (1 << 2))
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#define MR2_DYNAMIC_ODT_MASK (3 << 9)
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#define MR2_DYNAMIC_ODT_OFF (0 << 9)
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#define MR2_SELF_REFRESH_TEMP_MASK (1 << 7)
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#define MR2_SELF_REFRESH_TEMP_EXT (1 << 7)
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/**
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* Set certain fields of the JEDEC MR1 register.
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*/
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void cdns_ddr_set_mr1(void *base, int cs, u16 odt_impedance, u16 drive_strength);
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/**
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* Set certain fields of the JEDEC MR2 register.
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*/
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void cdns_ddr_set_mr2(void *base, int cs, u16 dynamic_odt, u16 self_refresh_temp);
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/**
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* Set ODT map of the DDR Controller.
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*/
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void cdns_ddr_set_odt_map(void *base, int cs, u16 odt_map);
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/**
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* Set ODT settings in the DDR Controller.
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*/
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void cdns_ddr_set_odt_times(void *base, u8 TODTL_2CMD, u8 TODTH_WR, u8 TODTH_RD,
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u8 WR_TO_ODTH, u8 RD_TO_ODTH);
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void cdns_ddr_set_same_cs_delays(void *base, u8 r2r, u8 r2w, u8 w2r, u8 w2w);
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void cdns_ddr_set_diff_cs_delays(void *base, u8 r2r, u8 r2w, u8 w2r, u8 w2w);
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#endif
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