Marek Vasut 8df653c325 ARM: socfpga: Factor out handoff register configuration ...

Factor out the code for programming preloader handoff register values,
the ISWGRP Handoff 0 and 1. These registers later control which bridges
are enabled by the "bridge" command on Gen5 devices.

Signed-off-by: Marek Vasut <marex@denx.de>
Cc: Chin Liang See <chin.liang.see@intel.com>
Cc: Dinh Nguyen <dinguyen@kernel.org>
Cc: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
Cc: Tien Fong Chee <tien.fong.chee@intel.com>

2019-04-29 10:08:55 +02:00

..

base_addr_a10.h

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2018-05-07 09:34:12 -04:00

base_addr_ac5.h

arm: socfpga: fix SPL booting from fpga OnChip RAM

2018-11-29 12:45:15 +01:00

base_addr_s10.h

arm: socfpga: stratix10: Add watchdog and firewall base addresses

2018-05-18 10:30:47 +02:00

boot0.h

ARM: socfpga: Add boot trampoline for Arria10

2018-05-08 21:08:42 +02:00

clock_manager_arria10.h

ARM: socfpga: Reorder Arria10 SPL

2018-08-24 12:05:20 +02:00

clock_manager_gen5.h

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2018-05-07 09:34:12 -04:00

clock_manager_s10.h

arm: socfpga: stratix10: Add clock manager driver for Stratix10 SoC

2018-05-18 10:30:47 +02:00

clock_manager.h

arm: socfpga: stratix10: Add clock manager driver for Stratix10 SoC

2018-05-18 10:30:47 +02:00

firewall_s10.h

arm: socfpga: stratix10: Add SPL driver for Stratix10 SoC

2018-07-12 09:22:12 +02:00

fpga_manager_arria10.h

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2018-05-07 09:34:12 -04:00

fpga_manager_gen5.h

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2018-05-07 09:34:12 -04:00

fpga_manager.h

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2018-05-07 09:34:12 -04:00

freeze_controller.h

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2018-05-07 09:34:12 -04:00

gpio.h

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2018-05-07 09:34:12 -04:00

handoff_s10.h

arm: socfpga: stratix10: Add clock manager driver for Stratix10 SoC

2018-05-18 10:30:47 +02:00

mailbox_s10.h

arm: socfpga: stratix10: Add macros for mailbox's arguments

2018-12-20 17:12:25 +01:00

misc.h

arm: socfpga: stratix10: Add Stratix10 FPGA into FPGA device table

2018-12-20 17:12:25 +01:00

nic301.h

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2018-05-07 09:34:12 -04:00

pinmux.h

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2018-05-07 09:34:12 -04:00

reset_manager_arria10.h

ARM: socfpga: Zap unused reset code

2018-08-13 22:35:42 +02:00

reset_manager_gen5.h

ARM: socfpga: Factor out handoff register configuration

2019-04-29 10:08:55 +02:00

reset_manager_s10.h

arm: socfpga: stratix10: Add cpu_has_been_warmreset()

2019-04-17 22:20:17 +02:00

reset_manager.h

arm: socfpga: gen5: remove hacked ETH RST handling

2019-02-18 13:00:53 +01:00

scan_manager.h

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2018-05-07 09:34:12 -04:00

scu.h

ARM: socfpga: Fix Documentation errors in scu_registers

2018-05-18 10:30:47 +02:00

sdram_arria10.h

ARM: socfpga: Add DDR driver for Arria 10

2018-05-18 10:30:47 +02:00

sdram_gen5.h

arm: socfpga: move gen5 SDR driver to DM

2019-04-17 22:20:16 +02:00

sdram_s10.h

ddr: altera: Stratix10: Add ECC memory scrubbing

2019-04-17 22:20:17 +02:00

sdram.h

ARM: socfpga: Add DDR driver for Arria 10

2018-05-18 10:30:47 +02:00

system_manager_arria10.h

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2018-05-07 09:34:12 -04:00

system_manager_gen5.h

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2018-05-07 09:34:12 -04:00

system_manager_s10.h

arm: socfpga: Fix SYSMGR_FPGAINTF_EMACx bit mask

2018-08-15 12:41:09 +02:00

system_manager.h

arm: socfpga: stratix10: Add pinmux support for Stratix10 SoC

2018-05-18 10:30:48 +02:00

timer.h

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2018-05-07 09:34:12 -04:00