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c9309f40a6
This function is a no-op. Remove it. Signed-off-by: Sean Anderson <seanga2@gmail.com> Link: https://lore.kernel.org/r/20231216193843.2463779-3-seanga2@gmail.com
392 lines
11 KiB
C
392 lines
11 KiB
C
// SPDX-License-Identifier: GPL-2.0+
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/*
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* Meson AXG MIPI DPHY driver
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*
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* Copyright (C) 2018 Amlogic, Inc. All rights reserved
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* Copyright (C) 2020 BayLibre, SAS
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* Author: Neil Armstrong <narmstrong@baylibre.com>
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*/
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#include <common.h>
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#include <log.h>
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#include <malloc.h>
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#include <asm/io.h>
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#include <bitfield.h>
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#include <dm.h>
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#include <errno.h>
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#include <generic-phy.h>
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#include <regmap.h>
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#include <linux/delay.h>
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#include <power/regulator.h>
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#include <reset.h>
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#include <clk.h>
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#include <phy-mipi-dphy.h>
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#include <linux/bitops.h>
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#include <linux/compat.h>
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#include <linux/bitfield.h>
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#include <linux/time.h>
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/* [31] soft reset for the phy.
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* 1: reset. 0: dessert the reset.
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* [30] clock lane soft reset.
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* [29] data byte lane 3 soft reset.
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* [28] data byte lane 2 soft reset.
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* [27] data byte lane 1 soft reset.
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* [26] data byte lane 0 soft reset.
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* [25] mipi dsi pll clock selection.
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* 1: clock from fixed 850Mhz clock source. 0: from VID2 PLL.
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* [12] mipi HSbyteclk enable.
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* [11] mipi divider clk selection.
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* 1: select the mipi DDRCLKHS from clock divider.
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* 0: from PLL clock.
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* [10] mipi clock divider control.
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* 1: /4. 0: /2.
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* [9] mipi divider output enable.
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* [8] mipi divider counter enable.
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* [7] PLL clock enable.
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* [5] LPDT data endian.
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* 1 = transfer the high bit first. 0 : transfer the low bit first.
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* [4] HS data endian.
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* [3] force data byte lane in stop mode.
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* [2] force data byte lane 0 in receiver mode.
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* [1] write 1 to sync the txclkesc input. the internal logic have to
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* use txclkesc to decide Txvalid and Txready.
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* [0] enalbe the MIPI DPHY TxDDRClk.
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*/
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#define MIPI_DSI_PHY_CTRL 0x0
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/* [31] clk lane tx_hs_en control selection.
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* 1: from register. 0: use clk lane state machine.
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* [30] register bit for clock lane tx_hs_en.
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* [29] clk lane tx_lp_en contrl selection.
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* 1: from register. 0: from clk lane state machine.
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* [28] register bit for clock lane tx_lp_en.
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* [27] chan0 tx_hs_en control selection.
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* 1: from register. 0: from chan0 state machine.
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* [26] register bit for chan0 tx_hs_en.
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* [25] chan0 tx_lp_en control selection.
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* 1: from register. 0: from chan0 state machine.
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* [24] register bit from chan0 tx_lp_en.
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* [23] chan0 rx_lp_en control selection.
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* 1: from register. 0: from chan0 state machine.
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* [22] register bit from chan0 rx_lp_en.
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* [21] chan0 contention detection enable control selection.
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* 1: from register. 0: from chan0 state machine.
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* [20] register bit from chan0 contention dectection enable.
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* [19] chan1 tx_hs_en control selection.
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* 1: from register. 0: from chan0 state machine.
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* [18] register bit for chan1 tx_hs_en.
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* [17] chan1 tx_lp_en control selection.
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* 1: from register. 0: from chan0 state machine.
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* [16] register bit from chan1 tx_lp_en.
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* [15] chan2 tx_hs_en control selection.
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* 1: from register. 0: from chan0 state machine.
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* [14] register bit for chan2 tx_hs_en.
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* [13] chan2 tx_lp_en control selection.
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* 1: from register. 0: from chan0 state machine.
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* [12] register bit from chan2 tx_lp_en.
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* [11] chan3 tx_hs_en control selection.
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* 1: from register. 0: from chan0 state machine.
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* [10] register bit for chan3 tx_hs_en.
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* [9] chan3 tx_lp_en control selection.
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* 1: from register. 0: from chan0 state machine.
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* [8] register bit from chan3 tx_lp_en.
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* [4] clk chan power down. this bit is also used as the power down
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* of the whole MIPI_DSI_PHY.
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* [3] chan3 power down.
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* [2] chan2 power down.
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* [1] chan1 power down.
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* [0] chan0 power down.
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*/
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#define MIPI_DSI_CHAN_CTRL 0x4
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/* [24] rx turn watch dog triggered.
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* [23] rx esc watchdog triggered.
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* [22] mbias ready.
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* [21] txclkesc synced and ready.
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* [20:17] clk lane state. {mbias_ready, tx_stop, tx_ulps, tx_hs_active}
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* [16:13] chan3 state{0, tx_stop, tx_ulps, tx_hs_active}
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* [12:9] chan2 state.{0, tx_stop, tx_ulps, tx_hs_active}
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* [8:5] chan1 state. {0, tx_stop, tx_ulps, tx_hs_active}
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* [4:0] chan0 state. {TX_STOP, tx_ULPS, hs_active, direction, rxulpsesc}
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*/
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#define MIPI_DSI_CHAN_STS 0x8
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/* [31:24] TCLK_PREPARE.
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* [23:16] TCLK_ZERO.
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* [15:8] TCLK_POST.
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* [7:0] TCLK_TRAIL.
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*/
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#define MIPI_DSI_CLK_TIM 0xc
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/* [31:24] THS_PREPARE.
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* [23:16] THS_ZERO.
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* [15:8] THS_TRAIL.
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* [7:0] THS_EXIT.
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*/
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#define MIPI_DSI_HS_TIM 0x10
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/* [31:24] tTA_GET.
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* [23:16] tTA_GO.
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* [15:8] tTA_SURE.
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* [7:0] tLPX.
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*/
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#define MIPI_DSI_LP_TIM 0x14
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/* wait time to MIPI DIS analog ready. */
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#define MIPI_DSI_ANA_UP_TIM 0x18
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/* TINIT. */
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#define MIPI_DSI_INIT_TIM 0x1c
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/* TWAKEUP. */
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#define MIPI_DSI_WAKEUP_TIM 0x20
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/* when in RxULPS check state, after the the logic enable the analog,
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* how long we should wait to check the lP state .
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*/
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#define MIPI_DSI_LPOK_TIM 0x24
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/* Watchdog for RX low power state no finished. */
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#define MIPI_DSI_LP_WCHDOG 0x28
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/* tMBIAS, after send power up signals to analog,
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* how long we should wait for analog powered up.
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*/
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#define MIPI_DSI_ANA_CTRL 0x2c
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/* [31:8] reserved for future.
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* [7:0] tCLK_PRE.
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*/
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#define MIPI_DSI_CLK_TIM1 0x30
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/* watchdog for turn around waiting time. */
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#define MIPI_DSI_TURN_WCHDOG 0x34
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/* When in RxULPS state, how frequency we should to check
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* if the TX side out of ULPS state.
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*/
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#define MIPI_DSI_ULPS_CHECK 0x38
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#define MIPI_DSI_TEST_CTRL0 0x3c
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#define MIPI_DSI_TEST_CTRL1 0x40
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struct phy_meson_axg_mipi_dphy_priv {
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struct regmap *regmap;
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#if CONFIG_IS_ENABLED(CLK)
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struct clk clk;
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#endif
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struct reset_ctl reset;
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struct phy analog;
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struct phy_configure_opts_mipi_dphy config;
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};
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static int phy_meson_axg_mipi_dphy_configure(struct phy *phy, void *params)
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{
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struct udevice *dev = phy->dev;
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struct phy_meson_axg_mipi_dphy_priv *priv = dev_get_priv(dev);
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struct phy_configure_opts_mipi_dphy *config = params;
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int ret;
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ret = phy_mipi_dphy_config_validate(config);
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if (ret)
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return ret;
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ret = generic_phy_configure(&priv->analog, config);
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if (ret)
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return ret;
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memcpy(&priv->config, config, sizeof(priv->config));
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return 0;
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}
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static int phy_meson_axg_mipi_dphy_power_on(struct phy *phy)
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{
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struct udevice *dev = phy->dev;
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struct phy_meson_axg_mipi_dphy_priv *priv = dev_get_priv(dev);
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unsigned long temp;
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int ret;
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ret = generic_phy_power_on(&priv->analog);
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if (ret)
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return ret;
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/* enable phy clock */
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regmap_write(priv->regmap, MIPI_DSI_PHY_CTRL, 0x1);
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regmap_write(priv->regmap, MIPI_DSI_PHY_CTRL,
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BIT(0) | /* enable the DSI PLL clock . */
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BIT(7) | /* enable pll clock which connected to DDR clock path */
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BIT(8)); /* enable the clock divider counter */
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/* enable the divider clock out */
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regmap_update_bits(priv->regmap, MIPI_DSI_PHY_CTRL, BIT(9), BIT(9));
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/* enable the byte clock generation. */
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regmap_update_bits(priv->regmap, MIPI_DSI_PHY_CTRL, BIT(12), BIT(12));
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regmap_update_bits(priv->regmap, MIPI_DSI_PHY_CTRL, BIT(31), BIT(31));
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regmap_update_bits(priv->regmap, MIPI_DSI_PHY_CTRL, BIT(31), 0);
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/* Calculate lanebyteclk period in ps */
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temp = (1000000 * 100) / (priv->config.hs_clk_rate / 1000);
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temp = temp * 8 * 10;
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regmap_write(priv->regmap, MIPI_DSI_CLK_TIM,
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DIV_ROUND_UP(priv->config.clk_trail, temp) |
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(DIV_ROUND_UP(priv->config.clk_post +
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priv->config.hs_trail, temp) << 8) |
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(DIV_ROUND_UP(priv->config.clk_zero, temp) << 16) |
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(DIV_ROUND_UP(priv->config.clk_prepare, temp) << 24));
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regmap_write(priv->regmap, MIPI_DSI_CLK_TIM1,
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DIV_ROUND_UP(priv->config.clk_pre, temp));
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regmap_write(priv->regmap, MIPI_DSI_HS_TIM,
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DIV_ROUND_UP(priv->config.hs_exit, temp) |
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(DIV_ROUND_UP(priv->config.hs_trail, temp) << 8) |
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(DIV_ROUND_UP(priv->config.hs_zero, temp) << 16) |
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(DIV_ROUND_UP(priv->config.hs_prepare, temp) << 24));
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regmap_write(priv->regmap, MIPI_DSI_LP_TIM,
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DIV_ROUND_UP(priv->config.lpx, temp) |
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(DIV_ROUND_UP(priv->config.ta_sure, temp) << 8) |
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(DIV_ROUND_UP(priv->config.ta_go, temp) << 16) |
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(DIV_ROUND_UP(priv->config.ta_get, temp) << 24));
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regmap_write(priv->regmap, MIPI_DSI_ANA_UP_TIM, 0x0100);
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regmap_write(priv->regmap, MIPI_DSI_INIT_TIM,
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DIV_ROUND_UP(priv->config.init * NSEC_PER_MSEC, temp));
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regmap_write(priv->regmap, MIPI_DSI_WAKEUP_TIM,
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DIV_ROUND_UP(priv->config.wakeup * NSEC_PER_MSEC, temp));
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regmap_write(priv->regmap, MIPI_DSI_LPOK_TIM, 0x7C);
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regmap_write(priv->regmap, MIPI_DSI_ULPS_CHECK, 0x927C);
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regmap_write(priv->regmap, MIPI_DSI_LP_WCHDOG, 0x1000);
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regmap_write(priv->regmap, MIPI_DSI_TURN_WCHDOG, 0x1000);
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/* Powerup the analog circuit */
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switch (priv->config.lanes) {
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case 1:
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regmap_write(priv->regmap, MIPI_DSI_CHAN_CTRL, 0xe);
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break;
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case 2:
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regmap_write(priv->regmap, MIPI_DSI_CHAN_CTRL, 0xc);
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break;
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case 3:
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regmap_write(priv->regmap, MIPI_DSI_CHAN_CTRL, 0x8);
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break;
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case 4:
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default:
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regmap_write(priv->regmap, MIPI_DSI_CHAN_CTRL, 0);
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break;
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}
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/* Trigger a sync active for esc_clk */
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regmap_update_bits(priv->regmap, MIPI_DSI_PHY_CTRL, BIT(1), BIT(1));
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return 0;
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}
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static int phy_meson_axg_mipi_dphy_power_off(struct phy *phy)
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{
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struct udevice *dev = phy->dev;
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struct phy_meson_axg_mipi_dphy_priv *priv = dev_get_priv(dev);
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regmap_write(priv->regmap, MIPI_DSI_CHAN_CTRL, 0xf);
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regmap_write(priv->regmap, MIPI_DSI_PHY_CTRL, BIT(31));
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return generic_phy_power_off(&priv->analog);
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}
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static int phy_meson_axg_mipi_dphy_init(struct phy *phy)
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{
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struct udevice *dev = phy->dev;
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struct phy_meson_axg_mipi_dphy_priv *priv = dev_get_priv(dev);
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int ret;
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ret = generic_phy_init(&priv->analog);
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if (ret)
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return ret;
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ret = reset_assert(&priv->reset);
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udelay(1);
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ret |= reset_deassert(&priv->reset);
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if (ret)
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return ret;
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return 0;
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}
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static int phy_meson_axg_mipi_dphy_exit(struct phy *phy)
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{
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struct udevice *dev = phy->dev;
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struct phy_meson_axg_mipi_dphy_priv *priv = dev_get_priv(dev);
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int ret;
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ret = generic_phy_exit(&priv->analog);
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if (ret)
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return ret;
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return reset_assert(&priv->reset);
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}
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struct phy_ops meson_axg_mipi_dphy_ops = {
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.init = phy_meson_axg_mipi_dphy_init,
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.exit = phy_meson_axg_mipi_dphy_exit,
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.power_on = phy_meson_axg_mipi_dphy_power_on,
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.power_off = phy_meson_axg_mipi_dphy_power_off,
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.configure = phy_meson_axg_mipi_dphy_configure,
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};
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int meson_axg_mipi_dphy_probe(struct udevice *dev)
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{
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struct phy_meson_axg_mipi_dphy_priv *priv = dev_get_priv(dev);
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int ret;
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ret = regmap_init_mem(dev_ofnode(dev), &priv->regmap);
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if (ret)
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return ret;
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ret = generic_phy_get_by_index(dev, 0, &priv->analog);
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if (ret)
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return ret;
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ret = reset_get_by_index(dev, 0, &priv->reset);
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if (ret == -ENOTSUPP)
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return 0;
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else if (ret)
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return ret;
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ret = reset_deassert(&priv->reset);
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if (ret) {
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reset_release_all(&priv->reset, 1);
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return ret;
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}
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#if CONFIG_IS_ENABLED(CLK)
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ret = clk_get_by_index(dev, 0, &priv->clk);
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if (ret < 0)
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return ret;
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ret = clk_enable(&priv->clk);
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if (ret && ret != -ENOSYS && ret != -ENOTSUPP) {
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pr_err("failed to enable PHY clock\n");
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return ret;
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}
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#endif
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return 0;
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}
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static const struct udevice_id meson_axg_mipi_dphy_ids[] = {
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{ .compatible = "amlogic,axg-mipi-dphy" },
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{ }
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};
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U_BOOT_DRIVER(meson_axg_mipi_dphy) = {
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.name = "meson_axg_mipi_dphy",
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.id = UCLASS_PHY,
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.of_match = meson_axg_mipi_dphy_ids,
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.probe = meson_axg_mipi_dphy_probe,
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.ops = &meson_axg_mipi_dphy_ops,
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.priv_auto = sizeof(struct phy_meson_axg_mipi_dphy_priv),
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};
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