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				https://xff.cz/git/u-boot/
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	As part of bringing the master branch back in to next, we need to allow for all of these changes to exist here. Reported-by: Jonas Karlman <jonas@kwiboo.se> Signed-off-by: Tom Rini <trini@konsulko.com>
		
			
				
	
	
		
			168 lines
		
	
	
		
			4.3 KiB
		
	
	
	
		
			C
		
	
	
	
	
	
			
		
		
	
	
			168 lines
		
	
	
		
			4.3 KiB
		
	
	
	
		
			C
		
	
	
	
	
	
| // SPDX-License-Identifier: GPL-2.0+
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| /*
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|  * Qualcomm GPIO driver
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|  *
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|  * (C) Copyright 2015 Mateusz Kulikowski <mateusz.kulikowski@gmail.com>
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|  */
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| 
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| #include <dm.h>
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| #include <errno.h>
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| #include <asm/global_data.h>
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| #include <asm/gpio.h>
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| #include <asm/io.h>
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| #include <mach/gpio.h>
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| 
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| DECLARE_GLOBAL_DATA_PTR;
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| 
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| /* OE */
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| #define GPIO_OE_DISABLE  (0x0 << 9)
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| #define GPIO_OE_ENABLE   (0x1 << 9)
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| #define GPIO_OE_MASK     (0x1 << 9)
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| 
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| /* GPIO_IN_OUT register shifts. */
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| #define GPIO_IN          0
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| #define GPIO_OUT         1
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| 
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| struct msm_gpio_bank {
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| 	phys_addr_t base;
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| 	const struct msm_pin_data *pin_data;
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| };
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| 
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| #define GPIO_CONFIG_REG(dev, x) \
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| 	(qcom_pin_offset(((struct msm_gpio_bank *)dev_get_priv(dev))->pin_data->pin_offsets, x))
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| 
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| #define GPIO_IN_OUT_REG(dev, x) \
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| 	(GPIO_CONFIG_REG(dev, x) + 0x4)
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| 
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| static void msm_gpio_direction_input(struct udevice *dev, unsigned int gpio)
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| {
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| 	struct msm_gpio_bank *priv = dev_get_priv(dev);
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| 
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| 	/* Always NOP for special pins, assume they're in the correct state */
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| 	if (qcom_is_special_pin(priv->pin_data, gpio))
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| 		return;
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| 
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| 	/* Disable OE bit */
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| 	clrsetbits_le32(priv->base + GPIO_CONFIG_REG(dev, gpio),
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| 			GPIO_OE_MASK, GPIO_OE_DISABLE);
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| 
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| 	return;
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| }
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| 
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| static int msm_gpio_set_value(struct udevice *dev, unsigned int gpio, int value)
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| {
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| 	struct msm_gpio_bank *priv = dev_get_priv(dev);
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| 
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| 	/* Always NOP for special pins, assume they're in the correct state */
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| 	if (qcom_is_special_pin(priv->pin_data, gpio))
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| 		return 0;
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| 
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| 	value = !!value;
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| 	/* set value */
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| 	writel(value << GPIO_OUT, priv->base + GPIO_IN_OUT_REG(dev, gpio));
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| 
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| 	return 0;
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| }
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| 
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| static int msm_gpio_direction_output(struct udevice *dev, unsigned int gpio,
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| 				     int value)
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| {
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| 	struct msm_gpio_bank *priv = dev_get_priv(dev);
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| 
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| 	/* Always NOP for special pins, assume they're in the correct state */
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| 	if (qcom_is_special_pin(priv->pin_data, gpio))
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| 		return 0;
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| 
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| 	value = !!value;
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| 	/* set value */
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| 	writel(value << GPIO_OUT, priv->base + GPIO_IN_OUT_REG(dev, gpio));
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| 	/* switch direction */
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| 	clrsetbits_le32(priv->base + GPIO_CONFIG_REG(dev, gpio),
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| 			GPIO_OE_MASK, GPIO_OE_ENABLE);
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| 
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| 	return 0;
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| }
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| 
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| static int msm_gpio_set_flags(struct udevice *dev, unsigned int gpio, ulong flags)
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| {
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| 	if (flags & GPIOD_IS_OUT_ACTIVE) {
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| 		return msm_gpio_direction_output(dev, gpio, 1);
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| 	} else if (flags & GPIOD_IS_OUT) {
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| 		return msm_gpio_direction_output(dev, gpio, 0);
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| 	} else if (flags & GPIOD_IS_IN) {
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| 		msm_gpio_direction_input(dev, gpio);
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| 		if (flags & GPIOD_PULL_UP)
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| 			return msm_gpio_set_value(dev, gpio, 1);
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| 		else if (flags & GPIOD_PULL_DOWN)
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| 			return msm_gpio_set_value(dev, gpio, 0);
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| 	}
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| 
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| 	return 0;
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| }
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| 
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| static int msm_gpio_get_value(struct udevice *dev, unsigned int gpio)
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| {
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| 	struct msm_gpio_bank *priv = dev_get_priv(dev);
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| 
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| 	/* Always NOP for special pins, assume they're in the correct state */
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| 	if (qcom_is_special_pin(priv->pin_data, gpio))
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| 		return 0;
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| 
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| 	return !!(readl(priv->base + GPIO_IN_OUT_REG(dev, gpio)) >> GPIO_IN);
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| }
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| 
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| static int msm_gpio_get_function(struct udevice *dev, unsigned int gpio)
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| {
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| 	struct msm_gpio_bank *priv = dev_get_priv(dev);
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| 
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| 	/* Always NOP for special pins, assume they're in the correct state */
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| 	if (qcom_is_special_pin(priv->pin_data, gpio))
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| 		return 0;
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| 
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| 	if (readl(priv->base + GPIO_CONFIG_REG(dev, gpio)) & GPIO_OE_ENABLE)
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| 		return GPIOF_OUTPUT;
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| 
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| 	return GPIOF_INPUT;
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| }
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| 
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| static const struct dm_gpio_ops gpio_msm_ops = {
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| 	.set_flags		= msm_gpio_set_flags,
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| 	.get_value		= msm_gpio_get_value,
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| 	.get_function		= msm_gpio_get_function,
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| };
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| 
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| static int msm_gpio_probe(struct udevice *dev)
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| {
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| 	struct msm_gpio_bank *priv = dev_get_priv(dev);
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| 
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| 	priv->base = dev_read_addr(dev);
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| 	priv->pin_data = (struct msm_pin_data *)dev_get_driver_data(dev);
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| 
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| 	return priv->base == FDT_ADDR_T_NONE ? -EINVAL : 0;
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| }
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| 
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| static int msm_gpio_of_to_plat(struct udevice *dev)
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| {
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| 	struct gpio_dev_priv *uc_priv = dev_get_uclass_priv(dev);
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| 	const struct msm_pin_data *pin_data = (struct msm_pin_data *)dev_get_driver_data(dev);
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| 
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| 	/* Get the pin count from the pinctrl driver */
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| 	uc_priv->gpio_count = pin_data->pin_count;
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| 	uc_priv->bank_name = fdt_getprop(gd->fdt_blob, dev_of_offset(dev),
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| 					 "gpio-bank-name", NULL);
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| 	if (uc_priv->bank_name == NULL)
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| 		uc_priv->bank_name = "soc";
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| 
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| 	return 0;
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| }
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| 
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| U_BOOT_DRIVER(gpio_msm) = {
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| 	.name	= "gpio_msm",
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| 	.id	= UCLASS_GPIO,
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| 	.of_to_plat = msm_gpio_of_to_plat,
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| 	.probe	= msm_gpio_probe,
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| 	.ops	= &gpio_msm_ops,
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| 	.flags	= DM_UC_FLAG_SEQ_ALIAS,
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| 	.priv_auto	= sizeof(struct msm_gpio_bank),
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| };
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