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c3880e6597
The USB peripheral controller is the DWC2 controller 1, not 0. Update the phandle to fix UDC support on this board. Signed-off-by: Marek Vasut <marex@denx.de> Cc: Siew Chin Lim <elly.siew.chin.lim@intel.com> Cc: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Cc: Tien Fong Chee <tien.fong.chee@intel.com>
59 lines
761 B
Plaintext
59 lines
761 B
Plaintext
// SPDX-License-Identifier: (GPL-2.0+ OR X11)
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/*
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* U-Boot additions
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*
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* Copyright (C) 2015 Marek Vasut <marex@denx.de>
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* Copyright (c) 2018 Simon Goldschmidt
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*/
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#include "socfpga-common-u-boot.dtsi"
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/{
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aliases {
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spi0 = "/soc/spi@ff705000";
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udc0 = &usb1;
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};
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};
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&mmc {
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status = "disabled";
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};
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&qspi {
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u-boot,dm-pre-reloc;
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n25q128@0 {
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compatible = "n25q128", "jedec,spi-nor";
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u-boot,dm-pre-reloc;
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};
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n25q00@1 {
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compatible = "n25q00", "jedec,spi-nor";
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u-boot,dm-pre-reloc;
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};
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};
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&uart0 {
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clock-frequency = <100000000>;
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u-boot,dm-pre-reloc;
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};
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&uart1 {
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clock-frequency = <100000000>;
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};
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&porta {
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bank-name = "porta";
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};
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&portb {
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bank-name = "portb";
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};
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&portc {
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bank-name = "portc";
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};
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&watchdog0 {
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u-boot,dm-pre-reloc;
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};
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