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b77026225a
Support of the MINI2440 board from FriendlyARM from an old version of u-boot : http://repo.or.cz/r/u-boot-openmoko/mini2440.git Currently, supporting only boot from NOR. Signed-off-by: Gabriel Huau <contact@huau-gabriel.fr>
135 lines
3.5 KiB
C
135 lines
3.5 KiB
C
/*
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* (C) Copyright 2002
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* Sysgo Real-Time Solutions, GmbH <www.elinos.com>
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* Marius Groeger <mgroeger@sysgo.de>
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*
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* (C) Copyright 2002
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* David Mueller, ELSOFT AG, <d.mueller@elsoft.ch>
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*
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* (C) Copyright 2009
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* Michel Pollet <buserror@gmail.com>
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*
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* (C) Copyright 2012
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* Gabriel Huau <contact@huau-gabriel.fr>
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*
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* See file CREDITS for list of people who contributed to this
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* project.
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License as
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* published by the Free Software Foundation; either version 2 of
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* the License, or (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
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* MA 02111-1307 USA
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*/
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#include <common.h>
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#include <asm/arch/s3c2440.h>
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#include <asm/arch/iomux.h>
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#include <asm/arch/gpio.h>
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#include <asm/io.h>
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#include <asm/gpio.h>
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#include <netdev.h>
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#include "mini2440.h"
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DECLARE_GLOBAL_DATA_PTR;
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static inline void pll_delay(unsigned long loops)
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{
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__asm__ volatile ("1:\n"
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"subs %0, %1, #1\n"
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"bne 1b" : "=r" (loops) : "0" (loops));
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}
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int board_early_init_f(void)
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{
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struct s3c24x0_clock_power * const clk_power =
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s3c24x0_get_base_clock_power();
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/* to reduce PLL lock time, adjust the LOCKTIME register */
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clk_power->locktime = 0xFFFFFF; /* Max PLL Lock time count */
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clk_power->clkdivn = CLKDIVN_VAL;
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/* configure UPLL */
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clk_power->upllcon = ((U_M_MDIV << 12) + (U_M_PDIV << 4) + U_M_SDIV);
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/* some delay between MPLL and UPLL */
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pll_delay(100);
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/* configure MPLL */
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clk_power->mpllcon = ((M_MDIV << 12) + (M_PDIV << 4) + M_SDIV);
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/* some delay between MPLL and UPLL */
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pll_delay(10000);
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return 0;
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}
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/*
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* Miscellaneous platform dependent initialisations
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*/
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int board_init(void)
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{
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struct s3c24x0_gpio * const gpio = s3c24x0_get_base_gpio();
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/* IOMUX Port H : UART Configuration */
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gpio->gphcon = IOMUXH_nCTS0 | IOMUXH_nRTS0 | IOMUXH_TXD0 | IOMUXH_RXD0 |
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IOMUXH_TXD1 | IOMUXH_RXD1 | IOMUXH_TXD2 | IOMUXH_RXD2;
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gpio_direction_output(GPH8, 0);
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gpio_direction_output(GPH9, 0);
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gpio_direction_output(GPH10, 0);
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/* adress of boot parameters */
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gd->bd->bi_boot_params = CONFIG_BOOT_PARAM_ADDR;
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return 0;
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}
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int dram_init(void)
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{
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struct s3c24x0_memctl *memctl = s3c24x0_get_base_memctl();
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/*
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* Configuring bus width and timing
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* Initialize clocks for each bank 0..5
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* Bank 3 and 4 are used for DM9000
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*/
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writel(BANK_CONF, &memctl->bwscon);
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writel(B0_CONF, &memctl->bankcon[0]);
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writel(B1_CONF, &memctl->bankcon[1]);
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writel(B2_CONF, &memctl->bankcon[2]);
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writel(B3_CONF, &memctl->bankcon[3]);
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writel(B4_CONF, &memctl->bankcon[4]);
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writel(B5_CONF, &memctl->bankcon[5]);
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/* Bank 6 and 7 are used for DRAM */
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writel(SDRAM_64MB, &memctl->bankcon[6]);
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writel(SDRAM_64MB, &memctl->bankcon[7]);
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writel(MEM_TIMING, &memctl->refresh);
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writel(BANKSIZE_CONF, &memctl->banksize);
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writel(B6_MRSR, &memctl->mrsrb6);
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writel(B7_MRSR, &memctl->mrsrb7);
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gd->ram_size = get_ram_size((void *) CONFIG_SYS_SDRAM_BASE,
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PHYS_SDRAM_SIZE);
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return 0;
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}
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int board_eth_init(bd_t *bis)
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{
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#ifdef CONFIG_DRIVER_DM9000
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return dm9000_initialize(bis);
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#else
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return 0;
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#endif
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}
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