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https://xff.cz/git/u-boot/
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2548493ab4
When you enable CONFIG_OF_LIVE, you will end up with a lot of conversions. To generate this commit, I used coccinelle excluding drivers/core/, include/dm/, and test/ The semantic patch that makes this change is as follows: <smpl> @@ expression dev; @@ -devfdt_get_addr(dev) +dev_read_addr(dev) </smpl> Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
121 lines
2.8 KiB
C
121 lines
2.8 KiB
C
// SPDX-License-Identifier: GPL-2.0+
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/*
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* UniPhier Specific Glue Layer for DWC3
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*
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* Copyright (C) 2016-2017 Socionext Inc.
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* Author: Masahiro Yamada <yamada.masahiro@socionext.com>
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*/
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#include <dm.h>
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#include <dm/device_compat.h>
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#include <linux/bitops.h>
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#include <linux/errno.h>
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#include <linux/io.h>
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#include <linux/sizes.h>
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#define UNIPHIER_PRO4_DWC3_RESET 0x40
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#define UNIPHIER_PRO4_DWC3_RESET_XIOMMU BIT(5)
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#define UNIPHIER_PRO4_DWC3_RESET_XLINK BIT(4)
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#define UNIPHIER_PRO4_DWC3_RESET_PHY_SS BIT(2)
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#define UNIPHIER_PRO5_DWC3_RESET 0x00
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#define UNIPHIER_PRO5_DWC3_RESET_PHY_S1 BIT(17)
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#define UNIPHIER_PRO5_DWC3_RESET_PHY_S0 BIT(16)
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#define UNIPHIER_PRO5_DWC3_RESET_XLINK BIT(15)
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#define UNIPHIER_PRO5_DWC3_RESET_XIOMMU BIT(14)
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#define UNIPHIER_PXS2_DWC3_RESET 0x00
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#define UNIPHIER_PXS2_DWC3_RESET_XLINK BIT(15)
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static int uniphier_pro4_dwc3_init(void __iomem *regs)
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{
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u32 tmp;
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tmp = readl(regs + UNIPHIER_PRO4_DWC3_RESET);
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tmp &= ~UNIPHIER_PRO4_DWC3_RESET_PHY_SS;
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tmp |= UNIPHIER_PRO4_DWC3_RESET_XIOMMU | UNIPHIER_PRO4_DWC3_RESET_XLINK;
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writel(tmp, regs + UNIPHIER_PRO4_DWC3_RESET);
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return 0;
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}
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static int uniphier_pro5_dwc3_init(void __iomem *regs)
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{
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u32 tmp;
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tmp = readl(regs + UNIPHIER_PRO5_DWC3_RESET);
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tmp &= ~(UNIPHIER_PRO5_DWC3_RESET_PHY_S1 |
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UNIPHIER_PRO5_DWC3_RESET_PHY_S0);
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tmp |= UNIPHIER_PRO5_DWC3_RESET_XLINK | UNIPHIER_PRO5_DWC3_RESET_XIOMMU;
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writel(tmp, regs + UNIPHIER_PRO5_DWC3_RESET);
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return 0;
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}
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static int uniphier_pxs2_dwc3_init(void __iomem *regs)
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{
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u32 tmp;
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tmp = readl(regs + UNIPHIER_PXS2_DWC3_RESET);
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tmp |= UNIPHIER_PXS2_DWC3_RESET_XLINK;
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writel(tmp, regs + UNIPHIER_PXS2_DWC3_RESET);
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return 0;
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}
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static int uniphier_dwc3_probe(struct udevice *dev)
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{
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fdt_addr_t base;
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void __iomem *regs;
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int (*init)(void __iomem *regs);
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int ret;
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base = dev_read_addr(dev);
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if (base == FDT_ADDR_T_NONE)
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return -EINVAL;
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regs = ioremap(base, SZ_32K);
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if (!regs)
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return -ENOMEM;
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init = (typeof(init))dev_get_driver_data(dev);
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ret = init(regs);
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if (ret)
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dev_err(dev, "failed to init glue layer\n");
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iounmap(regs);
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return ret;
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}
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static const struct udevice_id uniphier_dwc3_match[] = {
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{
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.compatible = "socionext,uniphier-pro4-dwc3",
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.data = (ulong)uniphier_pro4_dwc3_init,
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},
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{
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.compatible = "socionext,uniphier-pro5-dwc3",
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.data = (ulong)uniphier_pro5_dwc3_init,
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},
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{
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.compatible = "socionext,uniphier-pxs2-dwc3",
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.data = (ulong)uniphier_pxs2_dwc3_init,
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},
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{
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.compatible = "socionext,uniphier-ld20-dwc3",
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.data = (ulong)uniphier_pxs2_dwc3_init,
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},
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{
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.compatible = "socionext,uniphier-pxs3-dwc3",
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.data = (ulong)uniphier_pxs2_dwc3_init,
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},
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{ /* sentinel */ }
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};
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U_BOOT_DRIVER(usb_xhci) = {
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.name = "uniphier-dwc3",
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.id = UCLASS_SIMPLE_BUS,
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.of_match = uniphier_dwc3_match,
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.probe = uniphier_dwc3_probe,
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};
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