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174d728471
Update my and DPs email address to match current setup. Signed-off-by: Michal Simek <michal.simek@amd.com> Link: https://lore.kernel.org/r/aba5b19b9c5a95608829e86ad5cc4671c940f1bb.1688992543.git.michal.simek@amd.com
56 lines
1.2 KiB
C
56 lines
1.2 KiB
C
// SPDX-License-Identifier: GPL-2.0
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/*
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* (C) Copyright 2019, Xilinx, Inc,
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* Siva Durga Prasad Paladugu <siva.durga.prasad.paladugu@amd.com>>
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*/
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#include <common.h>
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#include <cpu_func.h>
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#include <log.h>
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#include <asm/arch/sys_proto.h>
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#include <memalign.h>
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#include <versalpl.h>
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#include <zynqmp_firmware.h>
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#include <asm/cache.h>
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static ulong versal_align_dma_buffer(ulong *buf, u32 len)
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{
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ulong *new_buf;
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if ((ulong)buf != ALIGN((ulong)buf, ARCH_DMA_MINALIGN)) {
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new_buf = (ulong *)ALIGN((ulong)buf, ARCH_DMA_MINALIGN);
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memcpy(new_buf, buf, len);
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buf = new_buf;
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}
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return (ulong)buf;
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}
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static int versal_load(xilinx_desc *desc, const void *buf, size_t bsize,
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bitstream_type bstype, int flags)
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{
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ulong bin_buf;
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int ret;
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u32 buf_lo, buf_hi;
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u32 ret_payload[PAYLOAD_ARG_CNT];
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bin_buf = versal_align_dma_buffer((ulong *)buf, bsize);
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debug("%s called!\n", __func__);
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flush_dcache_range(bin_buf, bin_buf + bsize);
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buf_lo = lower_32_bits(bin_buf);
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buf_hi = upper_32_bits(bin_buf);
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ret = xilinx_pm_request(VERSAL_PM_LOAD_PDI, VERSAL_PM_PDI_TYPE, buf_lo,
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buf_hi, 0, ret_payload);
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if (ret)
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printf("PL FPGA LOAD failed with err: 0x%08x\n", ret);
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return ret;
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}
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struct xilinx_fpga_op versal_op = {
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.load = versal_load,
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};
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