mirror of
https://xff.cz/git/u-boot/
synced 2025-09-02 01:02:19 +02:00
7b14cc991b
Update the ddrc Qos setting for B1 to align with B0's setting. Correct the initial clock for dram_pll. This setting will be overwrite before ddr phy training. Although there is no impact on the dram init, we still need to correct it to eliminate confusion. Signed-off-by: Bai Ping <ping.bai@nxp.com> Reviewed-by: Ye Li <ye.li@nxp.com> Tested-by: Robby Cai <robby.cai@nxp.com>