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449372148f
LS2080A is a prime personality of Freescale’s LS2085A. It is a non-AIOP personality without support of DP-DDR, L2 switch, 1588, PCIe endpoint etc. So renaming existing LS2085A code base to reflect LS2080A (Prime personality) Signed-off-by: Pratiyush Mohan Srivastava <pratiyush.srivastava@freescale.com> Signed-off-by: Prabhakar Kushwaha <prabhakar@freescale.com> [York Sun: Dropped #ifdef in cpu.c for cpu_type_list] Reviewed-by: York Sun <yorksun@freescale.com>
82 lines
2.5 KiB
C
82 lines
2.5 KiB
C
/*
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* Copyright 2015 Freescale Semiconductor, Inc.
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*
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* SPDX-License-Identifier: GPL-2.0+
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*/
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#include <common.h>
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#include <phy.h>
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#include <fsl-mc/ldpaa_wriop.h>
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#include <asm/io.h>
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#include <asm/arch/fsl_serdes.h>
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u32 dpmac_to_devdisr[] = {
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[WRIOP1_DPMAC1] = FSL_CHASSIS3_DEVDISR2_DPMAC1,
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[WRIOP1_DPMAC2] = FSL_CHASSIS3_DEVDISR2_DPMAC2,
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[WRIOP1_DPMAC3] = FSL_CHASSIS3_DEVDISR2_DPMAC3,
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[WRIOP1_DPMAC4] = FSL_CHASSIS3_DEVDISR2_DPMAC4,
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[WRIOP1_DPMAC5] = FSL_CHASSIS3_DEVDISR2_DPMAC5,
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[WRIOP1_DPMAC6] = FSL_CHASSIS3_DEVDISR2_DPMAC6,
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[WRIOP1_DPMAC7] = FSL_CHASSIS3_DEVDISR2_DPMAC7,
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[WRIOP1_DPMAC8] = FSL_CHASSIS3_DEVDISR2_DPMAC8,
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[WRIOP1_DPMAC9] = FSL_CHASSIS3_DEVDISR2_DPMAC9,
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[WRIOP1_DPMAC10] = FSL_CHASSIS3_DEVDISR2_DPMAC10,
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[WRIOP1_DPMAC11] = FSL_CHASSIS3_DEVDISR2_DPMAC11,
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[WRIOP1_DPMAC12] = FSL_CHASSIS3_DEVDISR2_DPMAC12,
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[WRIOP1_DPMAC13] = FSL_CHASSIS3_DEVDISR2_DPMAC13,
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[WRIOP1_DPMAC14] = FSL_CHASSIS3_DEVDISR2_DPMAC14,
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[WRIOP1_DPMAC15] = FSL_CHASSIS3_DEVDISR2_DPMAC15,
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[WRIOP1_DPMAC16] = FSL_CHASSIS3_DEVDISR2_DPMAC16,
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[WRIOP1_DPMAC17] = FSL_CHASSIS3_DEVDISR2_DPMAC17,
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[WRIOP1_DPMAC18] = FSL_CHASSIS3_DEVDISR2_DPMAC18,
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[WRIOP1_DPMAC19] = FSL_CHASSIS3_DEVDISR2_DPMAC19,
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[WRIOP1_DPMAC20] = FSL_CHASSIS3_DEVDISR2_DPMAC20,
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[WRIOP1_DPMAC21] = FSL_CHASSIS3_DEVDISR2_DPMAC21,
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[WRIOP1_DPMAC22] = FSL_CHASSIS3_DEVDISR2_DPMAC22,
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[WRIOP1_DPMAC23] = FSL_CHASSIS3_DEVDISR2_DPMAC23,
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[WRIOP1_DPMAC24] = FSL_CHASSIS3_DEVDISR2_DPMAC24,
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};
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static int is_device_disabled(int dpmac_id)
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{
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struct ccsr_gur __iomem *gur = (void *)CONFIG_SYS_FSL_GUTS_ADDR;
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u32 devdisr2 = in_le32(&gur->devdisr2);
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return dpmac_to_devdisr[dpmac_id] & devdisr2;
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}
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void wriop_dpmac_disable(int dpmac_id)
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{
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struct ccsr_gur __iomem *gur = (void *)CONFIG_SYS_FSL_GUTS_ADDR;
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setbits_le32(&gur->devdisr2, dpmac_to_devdisr[dpmac_id]);
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}
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void wriop_dpmac_enable(int dpmac_id)
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{
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struct ccsr_gur __iomem *gur = (void *)CONFIG_SYS_FSL_GUTS_ADDR;
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clrbits_le32(&gur->devdisr2, dpmac_to_devdisr[dpmac_id]);
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}
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phy_interface_t wriop_dpmac_enet_if(int dpmac_id, int lane_prtcl)
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{
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enum srds_prtcl;
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if (is_device_disabled(dpmac_id + 1))
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return PHY_INTERFACE_MODE_NONE;
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if (lane_prtcl >= SGMII1 && lane_prtcl <= SGMII16)
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return PHY_INTERFACE_MODE_SGMII;
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if (lane_prtcl >= XFI1 && lane_prtcl <= XFI8)
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return PHY_INTERFACE_MODE_XGMII;
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if (lane_prtcl >= XAUI1 && lane_prtcl <= XAUI2)
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return PHY_INTERFACE_MODE_XGMII;
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if (lane_prtcl >= QSGMII_A && lane_prtcl <= QSGMII_D)
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return PHY_INTERFACE_MODE_QSGMII;
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return PHY_INTERFACE_MODE_NONE;
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}
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