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d3ee9dbd59
Per NXP requirement, we rename all the NXP EdgeLock Secure Enclave code including comment, folder and API name to ELE to align. Signed-off-by: Peng Fan <peng.fan@nxp.com>
582 lines
13 KiB
C
582 lines
13 KiB
C
// SPDX-License-Identifier: GPL-2.0+
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/*
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* Copyright 2022 NXP
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*/
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#include <common.h>
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#include <log.h>
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#include <asm/io.h>
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#include <asm/types.h>
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#include <asm/arch/imx-regs.h>
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#include <asm/arch/sys_proto.h>
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#include <div64.h>
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#include <asm/mach-imx/ele_api.h>
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#include <asm/mach-imx/mu_hal.h>
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#define DID_NUM 16
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#define MBC_MAX_NUM 4
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#define MRC_MAX_NUM 2
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#define MBC_NUM(HWCFG) (((HWCFG) >> 16) & 0xF)
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#define MRC_NUM(HWCFG) (((HWCFG) >> 24) & 0x1F)
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struct mbc_mem_dom {
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u32 mem_glbcfg[4];
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u32 nse_blk_index;
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u32 nse_blk_set;
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u32 nse_blk_clr;
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u32 nsr_blk_clr_all;
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u32 memn_glbac[8];
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/* The upper only existed in the beginning of each MBC */
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u32 mem0_blk_cfg_w[64];
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u32 mem0_blk_nse_w[16];
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u32 mem1_blk_cfg_w[8];
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u32 mem1_blk_nse_w[2];
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u32 mem2_blk_cfg_w[8];
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u32 mem2_blk_nse_w[2];
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u32 mem3_blk_cfg_w[8];
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u32 mem3_blk_nse_w[2];/*0x1F0, 0x1F4 */
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u32 reserved[2];
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};
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struct mrc_rgn_dom {
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u32 mrc_glbcfg[4];
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u32 nse_rgn_indirect;
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u32 nse_rgn_set;
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u32 nse_rgn_clr;
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u32 nse_rgn_clr_all;
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u32 memn_glbac[8];
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/* The upper only existed in the beginning of each MRC */
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u32 rgn_desc_words[16][2]; /* 16 regions at max, 2 words per region */
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u32 rgn_nse;
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u32 reserved2[15];
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};
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struct mda_inst {
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u32 mda_w[8];
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};
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struct trdc_mgr {
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u32 trdc_cr;
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u32 res0[59];
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u32 trdc_hwcfg0;
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u32 trdc_hwcfg1;
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u32 res1[450];
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struct mda_inst mda[8];
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u32 res2[15808];
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};
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struct trdc_mbc {
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struct mbc_mem_dom mem_dom[DID_NUM];
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};
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struct trdc_mrc {
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struct mrc_rgn_dom mrc_dom[DID_NUM];
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};
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int trdc_mda_set_cpu(ulong trdc_reg, u32 mda_inst, u32 mda_reg, u8 sa, u8 dids,
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u8 did, u8 pe, u8 pidm, u8 pid)
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{
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struct trdc_mgr *trdc_base = (struct trdc_mgr *)trdc_reg;
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u32 *mda_w = &trdc_base->mda[mda_inst].mda_w[mda_reg];
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u32 val = readl(mda_w);
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if (val & BIT(29)) /* non-cpu */
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return -EINVAL;
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val = BIT(31) | ((pid & 0x3f) << 16) | ((pidm & 0x3f) << 8) |
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((pe & 0x3) << 6) | ((sa & 0x3) << 14) | ((dids & 0x3) << 4) |
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(did & 0xf);
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writel(val, mda_w);
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return 0;
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}
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int trdc_mda_set_noncpu(ulong trdc_reg, u32 mda_inst, u32 mda_reg,
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bool did_bypass, u8 sa, u8 pa, u8 did)
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{
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struct trdc_mgr *trdc_base = (struct trdc_mgr *)trdc_reg;
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u32 *mda_w = &trdc_base->mda[mda_inst].mda_w[mda_reg];
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u32 val = readl(mda_w);
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if (!(val & BIT(29))) /* cpu */
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return -EINVAL;
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val = BIT(31) | ((sa & 0x3) << 6) | ((pa & 0x3) << 4) | (did & 0xf);
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if (did_bypass)
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val |= BIT(8);
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writel(val, mda_w);
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return 0;
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}
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static ulong trdc_get_mbc_base(ulong trdc_reg, u32 mbc_x)
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{
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struct trdc_mgr *trdc_base = (struct trdc_mgr *)trdc_reg;
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u32 mbc_num = MBC_NUM(trdc_base->trdc_hwcfg0);
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if (mbc_x >= mbc_num)
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return 0;
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return trdc_reg + 0x10000 + 0x2000 * mbc_x;
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}
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static ulong trdc_get_mrc_base(ulong trdc_reg, u32 mrc_x)
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{
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struct trdc_mgr *trdc_base = (struct trdc_mgr *)trdc_reg;
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u32 mbc_num = MBC_NUM(trdc_base->trdc_hwcfg0);
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u32 mrc_num = MRC_NUM(trdc_base->trdc_hwcfg0);
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if (mrc_x >= mrc_num)
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return 0;
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return trdc_reg + 0x10000 + 0x2000 * mbc_num + 0x1000 * mrc_x;
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}
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int trdc_mbc_set_control(ulong trdc_reg, u32 mbc_x, u32 glbac_id, u32 glbac_val)
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{
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struct trdc_mbc *mbc_base = (struct trdc_mbc *)trdc_get_mbc_base(trdc_reg, mbc_x);
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struct mbc_mem_dom *mbc_dom;
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if (mbc_base == 0 || glbac_id >= 8)
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return -EINVAL;
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/* only first dom has the glbac */
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mbc_dom = &mbc_base->mem_dom[0];
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debug("mbc 0x%lx\n", (ulong)mbc_dom);
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writel(glbac_val, &mbc_dom->memn_glbac[glbac_id]);
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return 0;
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}
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int trdc_mbc_blk_config(ulong trdc_reg, u32 mbc_x, u32 dom_x, u32 mem_x,
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u32 blk_x, bool sec_access, u32 glbac_id)
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{
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struct trdc_mbc *mbc_base = (struct trdc_mbc *)trdc_get_mbc_base(trdc_reg, mbc_x);
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struct mbc_mem_dom *mbc_dom;
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u32 *cfg_w, *nse_w;
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u32 index, offset, val;
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if (mbc_base == 0 || glbac_id >= 8)
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return -EINVAL;
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mbc_dom = &mbc_base->mem_dom[dom_x];
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debug("mbc 0x%lx\n", (ulong)mbc_dom);
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switch (mem_x) {
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case 0:
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cfg_w = &mbc_dom->mem0_blk_cfg_w[blk_x / 8];
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nse_w = &mbc_dom->mem0_blk_nse_w[blk_x / 32];
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break;
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case 1:
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cfg_w = &mbc_dom->mem1_blk_cfg_w[blk_x / 8];
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nse_w = &mbc_dom->mem1_blk_nse_w[blk_x / 32];
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break;
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case 2:
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cfg_w = &mbc_dom->mem2_blk_cfg_w[blk_x / 8];
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nse_w = &mbc_dom->mem2_blk_nse_w[blk_x / 32];
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break;
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case 3:
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cfg_w = &mbc_dom->mem3_blk_cfg_w[blk_x / 8];
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nse_w = &mbc_dom->mem3_blk_nse_w[blk_x / 32];
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break;
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default:
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return -EINVAL;
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};
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index = blk_x % 8;
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offset = index * 4;
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val = readl((void __iomem *)cfg_w);
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val &= ~(0xFU << offset);
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/* MBC0-3
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* Global 0, 0x7777 secure pri/user read/write/execute, ELE has already set it.
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* So select MBC0_MEMN_GLBAC0
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*/
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if (sec_access) {
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val |= ((0x0 | (glbac_id & 0x7)) << offset);
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writel(val, (void __iomem *)cfg_w);
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} else {
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val |= ((0x8 | (glbac_id & 0x7)) << offset); /* nse bit set */
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writel(val, (void __iomem *)cfg_w);
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}
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return 0;
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}
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int trdc_mrc_set_control(ulong trdc_reg, u32 mrc_x, u32 glbac_id, u32 glbac_val)
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{
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struct trdc_mrc *mrc_base = (struct trdc_mrc *)trdc_get_mrc_base(trdc_reg, mrc_x);
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struct mrc_rgn_dom *mrc_dom;
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if (mrc_base == 0 || glbac_id >= 8)
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return -EINVAL;
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/* only first dom has the glbac */
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mrc_dom = &mrc_base->mrc_dom[0];
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debug("mrc_dom 0x%lx\n", (ulong)mrc_dom);
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writel(glbac_val, &mrc_dom->memn_glbac[glbac_id]);
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return 0;
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}
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int trdc_mrc_region_config(ulong trdc_reg, u32 mrc_x, u32 dom_x, u32 addr_start,
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u32 addr_end, bool sec_access, u32 glbac_id)
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{
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struct trdc_mrc *mrc_base = (struct trdc_mrc *)trdc_get_mrc_base(trdc_reg, mrc_x);
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struct mrc_rgn_dom *mrc_dom;
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u32 *desc_w;
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u32 start, end;
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u32 i, free = 8;
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bool vld, hit = false;
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if (mrc_base == 0 || glbac_id >= 8)
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return -EINVAL;
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mrc_dom = &mrc_base->mrc_dom[dom_x];
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addr_start &= ~0x3fff;
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addr_end &= ~0x3fff;
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debug("mrc_dom 0x%lx\n", (ulong)mrc_dom);
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for (i = 0; i < 8; i++) {
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desc_w = &mrc_dom->rgn_desc_words[i][0];
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debug("desc_w 0x%lx\n", (ulong)desc_w);
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start = readl((void __iomem *)desc_w) & (~0x3fff);
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end = readl((void __iomem *)(desc_w + 1));
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vld = end & 0x1;
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end = end & (~0x3fff);
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if (start == 0 && end == 0 && !vld && free >= 8)
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free = i;
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/* Check all the region descriptors, even overlap */
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if (addr_start >= end || addr_end <= start || !vld)
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continue;
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/* MRC0,1
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* Global 0, 0x7777 secure pri/user read/write/execute, ELE has already set it.
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* So select MRCx_MEMN_GLBAC0
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*/
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if (sec_access) {
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writel(start | (glbac_id & 0x7), (void __iomem *)desc_w);
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writel(end | 0x1, (void __iomem *)(desc_w + 1));
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} else {
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writel(start | (glbac_id & 0x7), (void __iomem *)desc_w);
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writel(end | 0x1 | 0x10, (void __iomem *)(desc_w + 1));
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}
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if (addr_start >= start && addr_end <= end)
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hit = true;
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}
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if (!hit) {
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if (free >= 8)
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return -EFAULT;
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desc_w = &mrc_dom->rgn_desc_words[free][0];
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debug("free desc_w 0x%lx\n", (ulong)desc_w);
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debug("[0x%x] [0x%x]\n", addr_start | (glbac_id & 0x7), addr_end | 0x1);
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if (sec_access) {
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writel(addr_start | (glbac_id & 0x7), (void __iomem *)desc_w);
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writel(addr_end | 0x1, (void __iomem *)(desc_w + 1));
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} else {
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writel(addr_start | (glbac_id & 0x7), (void __iomem *)desc_w);
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writel((addr_end | 0x1 | 0x10), (void __iomem *)(desc_w + 1));
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}
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}
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return 0;
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}
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bool trdc_mrc_enabled(ulong trdc_base)
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{
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return (!!(readl((void __iomem *)trdc_base) & 0x8000));
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}
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bool trdc_mbc_enabled(ulong trdc_base)
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{
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return (!!(readl((void __iomem *)trdc_base) & 0x4000));
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}
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int release_rdc(u8 xrdc)
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{
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ulong s_mu_base = 0x47520000UL;
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struct ele_msg msg;
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int ret;
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u32 rdc_id;
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switch (xrdc) {
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case 0:
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rdc_id = 0x74;
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break;
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case 1:
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rdc_id = 0x78;
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break;
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case 2:
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rdc_id = 0x82;
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break;
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case 3:
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rdc_id = 0x86;
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break;
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default:
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return -EINVAL;
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}
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msg.version = ELE_VERSION;
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msg.tag = ELE_CMD_TAG;
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msg.size = 2;
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msg.command = ELE_RELEASE_RDC_REQ;
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msg.data[0] = (rdc_id << 8) | 0x2; /* A55 */
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mu_hal_init(s_mu_base);
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mu_hal_sendmsg(s_mu_base, 0, *((u32 *)&msg));
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mu_hal_sendmsg(s_mu_base, 1, msg.data[0]);
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ret = mu_hal_receivemsg(s_mu_base, 0, (u32 *)&msg);
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if (!ret) {
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ret = mu_hal_receivemsg(s_mu_base, 1, &msg.data[0]);
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if (!ret) {
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if ((msg.data[0] & 0xff) == 0xd6)
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return 0;
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}
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return -EIO;
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}
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return ret;
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}
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void trdc_early_init(void)
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{
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int ret = 0, i;
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ret |= release_rdc(0);
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ret |= release_rdc(2);
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ret |= release_rdc(1);
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ret |= release_rdc(3);
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if (!ret) {
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/* Set OCRAM to RWX for secure, when OEM_CLOSE, the image is RX only */
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trdc_mbc_set_control(0x49010000, 3, 0, 0x7700);
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for (i = 0; i < 40; i++)
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trdc_mbc_blk_config(0x49010000, 3, 3, 0, i, true, 0);
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for (i = 0; i < 40; i++)
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trdc_mbc_blk_config(0x49010000, 3, 3, 1, i, true, 0);
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for (i = 0; i < 40; i++)
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trdc_mbc_blk_config(0x49010000, 3, 0, 0, i, true, 0);
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for (i = 0; i < 40; i++)
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trdc_mbc_blk_config(0x49010000, 3, 0, 1, i, true, 0);
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}
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}
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void trdc_init(void)
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{
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/* TRDC mega */
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if (trdc_mrc_enabled(0x49010000)) {
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/* DDR */
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trdc_mrc_set_control(0x49010000, 0, 0, 0x7777);
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/* ELE */
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trdc_mrc_region_config(0x49010000, 0, 0, 0x80000000, 0xFFFFFFFF, false, 0);
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/* MTR */
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trdc_mrc_region_config(0x49010000, 0, 1, 0x80000000, 0xFFFFFFFF, false, 0);
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/* M33 */
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trdc_mrc_region_config(0x49010000, 0, 2, 0x80000000, 0xFFFFFFFF, false, 0);
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/* A55*/
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trdc_mrc_region_config(0x49010000, 0, 3, 0x80000000, 0xFFFFFFFF, false, 0);
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/* For USDHC1 to DDR, USDHC1 is default force to non-secure */
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trdc_mrc_region_config(0x49010000, 0, 5, 0x80000000, 0xFFFFFFFF, false, 0);
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/* For USDHC2 to DDR, USDHC2 is default force to non-secure */
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trdc_mrc_region_config(0x49010000, 0, 6, 0x80000000, 0xFFFFFFFF, false, 0);
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/* eDMA */
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trdc_mrc_region_config(0x49010000, 0, 7, 0x80000000, 0xFFFFFFFF, false, 0);
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/*CoreSight, TestPort*/
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trdc_mrc_region_config(0x49010000, 0, 8, 0x80000000, 0xFFFFFFFF, false, 0);
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/* DAP */
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trdc_mrc_region_config(0x49010000, 0, 9, 0x80000000, 0xFFFFFFFF, false, 0);
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/*SoC masters */
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trdc_mrc_region_config(0x49010000, 0, 10, 0x80000000, 0xFFFFFFFF, false, 0);
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/*USB*/
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trdc_mrc_region_config(0x49010000, 0, 11, 0x80000000, 0xFFFFFFFF, false, 0);
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}
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}
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#if DEBUG
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int trdc_mbc_control_dump(ulong trdc_reg, u32 mbc_x, u32 glbac_id)
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{
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struct trdc_mbc *mbc_base = (struct trdc_mbc *)trdc_get_mbc_base(trdc_reg, mbc_x);
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struct mbc_mem_dom *mbc_dom;
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if (mbc_base == 0 || glbac_id >= 8)
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return -EINVAL;
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/* only first dom has the glbac */
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mbc_dom = &mbc_base->mem_dom[0];
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printf("mbc_dom %u glbac %u: 0x%x\n",
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mbc_x, glbac_id, readl(&mbc_dom->memn_glbac[glbac_id]));
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return 0;
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}
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int trdc_mbc_mem_dump(ulong trdc_reg, u32 mbc_x, u32 dom_x, u32 mem_x, u32 word)
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{
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struct trdc_mbc *mbc_base = (struct trdc_mbc *)trdc_get_mbc_base(trdc_reg, mbc_x);
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struct mbc_mem_dom *mbc_dom;
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u32 *cfg_w;
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if (mbc_base == 0)
|
|
return -EINVAL;
|
|
|
|
mbc_dom = &mbc_base->mem_dom[dom_x];
|
|
|
|
switch (mem_x) {
|
|
case 0:
|
|
cfg_w = &mbc_dom->mem0_blk_cfg_w[word];
|
|
break;
|
|
case 1:
|
|
cfg_w = &mbc_dom->mem1_blk_cfg_w[word];
|
|
break;
|
|
case 2:
|
|
cfg_w = &mbc_dom->mem2_blk_cfg_w[word];
|
|
break;
|
|
case 3:
|
|
cfg_w = &mbc_dom->mem3_blk_cfg_w[word];
|
|
break;
|
|
default:
|
|
return -EINVAL;
|
|
};
|
|
|
|
printf("mbc_dom %u dom %u mem %u word %u: 0x%x\n",
|
|
mbc_x, dom_x, mem_x, word, readl((void __iomem *)cfg_w));
|
|
|
|
return 0;
|
|
}
|
|
|
|
int trdc_mrc_control_dump(ulong trdc_reg, u32 mrc_x, u32 glbac_id)
|
|
{
|
|
struct trdc_mrc *mrc_base = (struct trdc_mrc *)trdc_get_mrc_base(trdc_reg, mrc_x);
|
|
struct mrc_rgn_dom *mrc_dom;
|
|
|
|
if (mrc_base == 0 || glbac_id >= 8)
|
|
return -EINVAL;
|
|
|
|
/* only first dom has the glbac */
|
|
mrc_dom = &mrc_base->mrc_dom[0];
|
|
|
|
printf("mrc_dom %u glbac %u: 0x%x\n",
|
|
mrc_x, glbac_id, readl(&mrc_dom->memn_glbac[glbac_id]));
|
|
|
|
return 0;
|
|
}
|
|
|
|
void trdc_dump(void)
|
|
{
|
|
u32 i;
|
|
|
|
printf("TRDC AONMIX MBC\n");
|
|
|
|
trdc_mbc_control_dump(0x44270000, 0, 0);
|
|
trdc_mbc_control_dump(0x44270000, 1, 0);
|
|
|
|
for (i = 0; i < 11; i++)
|
|
trdc_mbc_mem_dump(0x44270000, 0, 3, 0, i);
|
|
for (i = 0; i < 1; i++)
|
|
trdc_mbc_mem_dump(0x44270000, 0, 3, 1, i);
|
|
|
|
for (i = 0; i < 4; i++)
|
|
trdc_mbc_mem_dump(0x44270000, 1, 3, 0, i);
|
|
for (i = 0; i < 4; i++)
|
|
trdc_mbc_mem_dump(0x44270000, 1, 3, 1, i);
|
|
|
|
printf("TRDC WAKEUP MBC\n");
|
|
|
|
trdc_mbc_control_dump(0x42460000, 0, 0);
|
|
trdc_mbc_control_dump(0x42460000, 1, 0);
|
|
|
|
for (i = 0; i < 15; i++)
|
|
trdc_mbc_mem_dump(0x42460000, 0, 3, 0, i);
|
|
|
|
trdc_mbc_mem_dump(0x42460000, 0, 3, 1, 0);
|
|
trdc_mbc_mem_dump(0x42460000, 0, 3, 2, 0);
|
|
|
|
for (i = 0; i < 2; i++)
|
|
trdc_mbc_mem_dump(0x42460000, 1, 3, 0, i);
|
|
|
|
trdc_mbc_mem_dump(0x42460000, 1, 3, 1, 0);
|
|
trdc_mbc_mem_dump(0x42460000, 1, 3, 2, 0);
|
|
trdc_mbc_mem_dump(0x42460000, 1, 3, 3, 0);
|
|
|
|
printf("TRDC NICMIX MBC\n");
|
|
|
|
trdc_mbc_control_dump(0x49010000, 0, 0);
|
|
trdc_mbc_control_dump(0x49010000, 1, 0);
|
|
trdc_mbc_control_dump(0x49010000, 2, 0);
|
|
trdc_mbc_control_dump(0x49010000, 3, 0);
|
|
|
|
for (i = 0; i < 7; i++)
|
|
trdc_mbc_mem_dump(0x49010000, 0, 3, 0, i);
|
|
|
|
for (i = 0; i < 2; i++)
|
|
trdc_mbc_mem_dump(0x49010000, 0, 3, 1, i);
|
|
|
|
for (i = 0; i < 5; i++)
|
|
trdc_mbc_mem_dump(0x49010000, 0, 3, 2, i);
|
|
|
|
for (i = 0; i < 6; i++)
|
|
trdc_mbc_mem_dump(0x49010000, 0, 3, 3, i);
|
|
|
|
for (i = 0; i < 1; i++)
|
|
trdc_mbc_mem_dump(0x49010000, 1, 3, 0, i);
|
|
|
|
for (i = 0; i < 1; i++)
|
|
trdc_mbc_mem_dump(0x49010000, 1, 3, 1, i);
|
|
|
|
for (i = 0; i < 3; i++)
|
|
trdc_mbc_mem_dump(0x49010000, 1, 3, 2, i);
|
|
|
|
for (i = 0; i < 3; i++)
|
|
trdc_mbc_mem_dump(0x49010000, 1, 3, 3, i);
|
|
|
|
for (i = 0; i < 2; i++)
|
|
trdc_mbc_mem_dump(0x49010000, 2, 3, 0, i);
|
|
|
|
for (i = 0; i < 2; i++)
|
|
trdc_mbc_mem_dump(0x49010000, 2, 3, 1, i);
|
|
|
|
for (i = 0; i < 5; i++)
|
|
trdc_mbc_mem_dump(0x49010000, 3, 3, 0, i);
|
|
|
|
for (i = 0; i < 5; i++)
|
|
trdc_mbc_mem_dump(0x49010000, 3, 3, 1, i);
|
|
}
|
|
#endif
|