mirror of
https://xff.cz/git/u-boot/
synced 2025-10-31 18:35:42 +01:00
487fa1aa97
PPA was a secure firmware developed in-house which is no longer supported and replaced by TF-A quite some years ago. Drop support for it. Signed-off-by: Laurentiu Tudor <laurentiu.tudor@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
688 lines
17 KiB
Plaintext
688 lines
17 KiB
Plaintext
config ARCH_LS1012A
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bool
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select ARMV8_SET_SMPEN
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select ARM_ERRATA_855873 if !TFABOOT
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select FSL_LAYERSCAPE
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select FSL_LSCH2
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select GICV2
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select SKIP_LOWLEVEL_INIT
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select SYS_FSL_SRDS_1
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select SYS_HAS_SERDES
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select SYS_FSL_DDR_BE
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select SYS_FSL_MMDC
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select SYS_FSL_ERRATUM_A010315 if PCIE_LAYERSCAPE
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select SYS_FSL_ERRATUM_A009798
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select SYS_FSL_ERRATUM_A008997
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select SYS_FSL_ERRATUM_A009007
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select SYS_FSL_ERRATUM_A009008
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select ARCH_EARLY_INIT_R
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select BOARD_EARLY_INIT_F
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select SYS_I2C_MXC
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select SYS_I2C_MXC_I2C1 if !DM_I2C
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select SYS_I2C_MXC_I2C2 if !DM_I2C
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imply PANIC_HANG
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imply TIMESTAMP
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config ARCH_LS1028A
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bool
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select ARMV8_SET_SMPEN
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select ESBC_HDR_LS if CHAIN_OF_TRUST
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select FSL_LAYERSCAPE
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select FSL_LSCH3
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select FSL_TZASC_400
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select GICV3
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select NXP_LSCH3_2
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select SYS_FSL_HAS_CCI400
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select SYS_FSL_SRDS_1
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select SYS_HAS_SERDES
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select SYS_FSL_DDR
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select SYS_FSL_DDR_LE
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select SYS_FSL_DDR_VER_50
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select SYS_FSL_HAS_DDR3
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select SYS_FSL_HAS_DDR4
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select SYS_FSL_HAS_SEC
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select SYS_FSL_SEC_COMPAT_5
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select SYS_FSL_SEC_LE
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select FSL_TZASC_1
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select FSL_TZPC_BP147
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select ARCH_EARLY_INIT_R
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select BOARD_EARLY_INIT_F
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select SYS_I2C_MXC
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select SYS_FSL_ERRATUM_A008997
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select SYS_FSL_ERRATUM_A009007
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select SYS_FSL_ERRATUM_A008514 if !TFABOOT
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select SYS_FSL_ERRATUM_A009663 if !TFABOOT
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select SYS_FSL_ERRATUM_A009942 if !TFABOOT
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select SYS_FSL_ERRATUM_A050382
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select SYS_FSL_ERRATUM_A011334
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select SYS_FSL_ESDHC_UNRELIABLE_PULSE_DETECTION_WORKAROUND
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select RESV_RAM if GIC_V3_ITS
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select SYS_HAS_ARMV8_SECURE_BASE
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imply PANIC_HANG
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config ARCH_LS1043A
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bool
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select ARMV8_SET_SMPEN
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select ARM_ERRATA_855873 if !TFABOOT
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select FSL_IFC if TFABOOT || (!QSPI_BOOT && !SD_BOOT_QSPI && !SD_BOOT)
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select FSL_LAYERSCAPE
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select FSL_LSCH2
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select GICV2
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select HAS_FSL_XHCI_USB if USB_HOST
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select SKIP_LOWLEVEL_INIT
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select SYS_DPAA_FMAN
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select SYS_FSL_SRDS_1
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select SYS_HAS_SERDES
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select SYS_FSL_DDR
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select SYS_FSL_DDR_BE
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select SYS_FSL_DDR_VER_50
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select SYS_FSL_ERRATUM_A008850 if !TFABOOT
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select SYS_FSL_ERRATUM_A008997
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select SYS_FSL_ERRATUM_A009008
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select SYS_FSL_ERRATUM_A009660 if !TFABOOT
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select SYS_FSL_ERRATUM_A009663 if !TFABOOT
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select SYS_FSL_ERRATUM_A009798
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select SYS_FSL_ERRATUM_A009942 if !TFABOOT
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select SYS_FSL_ERRATUM_A010315 if PCIE_LAYERSCAPE
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select SYS_FSL_ERRATUM_A010539
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select SYS_FSL_HAS_DDR3
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select SYS_FSL_HAS_DDR4
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select SYS_FSL_QMAN_V3 if SYS_DPAA_QBMAN
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select ARCH_EARLY_INIT_R
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select BOARD_EARLY_INIT_F
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select SYS_I2C_MXC
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select SYS_I2C_MXC_I2C1 if !DM_I2C
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select SYS_I2C_MXC_I2C2 if !DM_I2C
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select SYS_I2C_MXC_I2C3 if !DM_I2C
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select SYS_I2C_MXC_I2C4 if !DM_I2C
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select SYS_HAS_ARMV8_SECURE_BASE
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imply CMD_PCI
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imply ID_EEPROM
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config ARCH_LS1046A
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bool
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select ARMV8_SET_SMPEN
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select FSL_IFC if TFABOOT || (!QSPI_BOOT && !SD_BOOT_QSPI && !SD_BOOT)
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select FSL_LAYERSCAPE
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select FSL_LSCH2
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select GICV2
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select HAS_FSL_XHCI_USB if USB_HOST
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select SKIP_LOWLEVEL_INIT
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select SYS_DPAA_FMAN
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select SYS_FSL_SRDS_1
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select SYS_HAS_SERDES
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select SYS_FSL_DDR
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select SYS_FSL_DDR_BE
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select SYS_FSL_DDR_VER_50
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select SYS_FSL_ERRATUM_A008336 if !TFABOOT
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select SYS_FSL_ERRATUM_A008511 if !TFABOOT
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select SYS_FSL_ERRATUM_A008850 if !TFABOOT
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select SYS_FSL_ERRATUM_A008997
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select SYS_FSL_ERRATUM_A009008
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select SYS_FSL_ERRATUM_A009798
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select SYS_FSL_ERRATUM_A009801
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select SYS_FSL_ERRATUM_A009803 if !TFABOOT
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select SYS_FSL_ERRATUM_A009942 if !TFABOOT
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select SYS_FSL_ERRATUM_A010165 if !TFABOOT
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select SYS_FSL_ERRATUM_A010539
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select SYS_FSL_HAS_DDR4
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select SYS_FSL_SRDS_2
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select SYS_FSL_QMAN_V3 if SYS_DPAA_QBMAN
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select ARCH_EARLY_INIT_R
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select BOARD_EARLY_INIT_F
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select SYS_I2C_MXC
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select SYS_I2C_MXC_I2C1 if !DM_I2C
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select SYS_I2C_MXC_I2C2 if !DM_I2C
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select SYS_I2C_MXC_I2C3 if !DM_I2C
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select SYS_I2C_MXC_I2C4 if !DM_I2C
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imply ID_EEPROM
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imply SCSI
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imply SCSI_AHCI
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imply SPL_SYS_I2C_LEGACY
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config ARCH_LS1088A
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bool
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select ARMV8_SET_SMPEN
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select ARM_ERRATA_855873 if !TFABOOT
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select ESBC_HDR_LS if CHAIN_OF_TRUST
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select FSL_IFC
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select FSL_LAYERSCAPE
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select FSL_LSCH3
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select GICV3
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select SKIP_LOWLEVEL_INIT
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select SYS_FSL_SRDS_1
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select SYS_HAS_SERDES
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select SYS_FSL_DDR
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select SYS_FSL_DDR_LE
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select SYS_FSL_DDR_VER_50
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select SYS_FSL_EC1
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select SYS_FSL_EC2
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select SYS_FSL_ERRATUM_A009803 if !TFABOOT
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select SYS_FSL_ERRATUM_A009942 if !TFABOOT
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select SYS_FSL_ERRATUM_A010165 if !TFABOOT
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select SYS_FSL_ERRATUM_A008511 if !TFABOOT
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select SYS_FSL_ERRATUM_A008850 if !TFABOOT
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select SYS_FSL_ERRATUM_A009007
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select SYS_FSL_HAS_CCI400
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select SYS_FSL_HAS_DDR4
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select SYS_FSL_HAS_RGMII
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select SYS_FSL_HAS_SEC
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select SYS_FSL_SEC_COMPAT_5
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select SYS_FSL_SEC_LE
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select SYS_FSL_SRDS_1
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select SYS_FSL_SRDS_2
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select FSL_TZASC_1
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select FSL_TZASC_400
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select FSL_TZPC_BP147
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select ARCH_EARLY_INIT_R
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select BOARD_EARLY_INIT_F
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select SYS_I2C_MXC
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select SYS_I2C_MXC_I2C1 if !TFABOOT
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select SYS_I2C_MXC_I2C2 if !TFABOOT
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select SYS_I2C_MXC_I2C3 if !TFABOOT
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select SYS_I2C_MXC_I2C4 if !TFABOOT
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select RESV_RAM if GIC_V3_ITS
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imply ID_EEPROM
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imply SCSI
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imply SPL_SYS_I2C_LEGACY
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imply PANIC_HANG
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config ARCH_LS2080A
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bool
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select ARMV8_SET_SMPEN
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select ARM_ERRATA_826974
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select ARM_ERRATA_828024
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select ARM_ERRATA_829520
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select ARM_ERRATA_833471
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select ESBC_HDR_LS if CHAIN_OF_TRUST
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select FSL_IFC
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select FSL_LAYERSCAPE
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select FSL_LSCH3
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select SYS_FSL_OTHER_DDR_NUM_CTRLS
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select GICV3
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select SKIP_LOWLEVEL_INIT
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select SYS_FSL_SRDS_1
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select SYS_HAS_SERDES
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select SYS_FSL_DDR
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select SYS_FSL_DDR_LE
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select SYS_FSL_DDR_VER_50
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select SYS_FSL_HAS_CCN504
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select SYS_FSL_HAS_DP_DDR
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select SYS_FSL_HAS_SEC
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select SYS_FSL_HAS_DDR4
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select SYS_FSL_SEC_COMPAT_5
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select SYS_FSL_SEC_LE
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select SYS_FSL_SRDS_2
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select FSL_TZASC_1
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select FSL_TZASC_2
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select FSL_TZASC_400
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select FSL_TZPC_BP147
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select SYS_FSL_ERRATUM_A008336 if !TFABOOT
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select SYS_FSL_ERRATUM_A008511 if !TFABOOT
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select SYS_FSL_ERRATUM_A008514 if !TFABOOT
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select SYS_FSL_ERRATUM_A008585
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select SYS_FSL_ERRATUM_A008997
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select SYS_FSL_ERRATUM_A009007
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select SYS_FSL_ERRATUM_A009008
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select SYS_FSL_ERRATUM_A009635
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select SYS_FSL_ERRATUM_A009663 if !TFABOOT
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select SYS_FSL_ERRATUM_A009798
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select SYS_FSL_ERRATUM_A009801
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select SYS_FSL_ERRATUM_A009803 if !TFABOOT
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select SYS_FSL_ERRATUM_A009942 if !TFABOOT
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select SYS_FSL_ERRATUM_A010165 if !TFABOOT
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select SYS_FSL_ERRATUM_A009203
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select ARCH_EARLY_INIT_R
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select BOARD_EARLY_INIT_F
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select SYS_I2C_MXC
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select SYS_I2C_MXC_I2C1 if !TFABOOT
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select SYS_I2C_MXC_I2C2 if !TFABOOT
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select SYS_I2C_MXC_I2C3 if !TFABOOT
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select SYS_I2C_MXC_I2C4 if !TFABOOT
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select RESV_RAM if GIC_V3_ITS
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imply DISTRO_DEFAULTS
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imply ID_EEPROM
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imply PANIC_HANG
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imply SPL_SYS_I2C_LEGACY
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config ARCH_LX2162A
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bool
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select ARMV8_SET_SMPEN
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select ESBC_HDR_LS if CHAIN_OF_TRUST
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select FSL_DDR_BIST
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select FSL_DDR_INTERACTIVE
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select FSL_LAYERSCAPE
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select FSL_LSCH3
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select FSL_TZPC_BP147
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select GICV3
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select NXP_LSCH3_2
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select SYS_HAS_SERDES
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select SYS_FSL_SRDS_1
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select SYS_FSL_SRDS_2
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select SYS_FSL_DDR
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select SYS_FSL_DDR_LE
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select SYS_FSL_DDR_VER_50
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select SYS_FSL_EC1
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select SYS_FSL_EC2
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select SYS_FSL_ERRATUM_A050204
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select SYS_FSL_ERRATUM_A011334
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select SYS_FSL_ESDHC_UNRELIABLE_PULSE_DETECTION_WORKAROUND
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select SYS_FSL_HAS_RGMII
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select SYS_FSL_HAS_SEC
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select SYS_FSL_HAS_CCN508
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select SYS_FSL_HAS_DDR4
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select SYS_FSL_SEC_COMPAT_5
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select SYS_FSL_SEC_LE
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select SYS_PCI_64BIT if PCI
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select ARCH_EARLY_INIT_R
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select BOARD_EARLY_INIT_F
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select SYS_I2C_MXC
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select RESV_RAM if GIC_V3_ITS
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imply DISTRO_DEFAULTS
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imply PANIC_HANG
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imply SCSI
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imply SCSI_AHCI
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imply SPL_SYS_I2C_LEGACY
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config ARCH_LX2160A
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bool
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select ARMV8_SET_SMPEN
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select ESBC_HDR_LS if CHAIN_OF_TRUST
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select FSL_DDR_BIST
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select FSL_DDR_INTERACTIVE
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select FSL_LAYERSCAPE
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select FSL_LSCH3
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select FSL_TZPC_BP147
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select GICV3
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select HAS_FSL_XHCI_USB if USB_HOST
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select NXP_LSCH3_2
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select SYS_HAS_SERDES
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select SYS_FSL_SRDS_1
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select SYS_FSL_SRDS_2
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select SYS_NXP_SRDS_3
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select SYS_FSL_DDR
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select SYS_FSL_DDR_LE
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select SYS_FSL_DDR_VER_50
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select SYS_FSL_EC1
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select SYS_FSL_EC2
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select SYS_FSL_ERRATUM_A050204
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select SYS_FSL_ERRATUM_A011334
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select SYS_FSL_ESDHC_UNRELIABLE_PULSE_DETECTION_WORKAROUND
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select SYS_FSL_HAS_RGMII
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select SYS_FSL_HAS_SEC
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select SYS_FSL_HAS_CCN508
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select SYS_FSL_HAS_DDR4
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select SYS_FSL_SEC_COMPAT_5
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select SYS_FSL_SEC_LE
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select SYS_PCI_64BIT if PCI
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select ARCH_EARLY_INIT_R
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select BOARD_EARLY_INIT_F
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select SYS_I2C_MXC
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select RESV_RAM if GIC_V3_ITS
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imply DISTRO_DEFAULTS
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imply ID_EEPROM
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imply PANIC_HANG
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imply SCSI
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imply SCSI_AHCI
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imply SPL_SYS_I2C_LEGACY
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config FSL_LSCH2
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bool
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select SKIP_LOWLEVEL_INIT
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select SYS_FSL_CCSR_GUR_BE
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select SYS_FSL_CCSR_SCFG_BE
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select SYS_FSL_ESDHC_BE
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select SYS_FSL_IFC_BE
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select SYS_FSL_PEX_LUT_BE
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select SYS_FSL_HAS_CCI400
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select SYS_FSL_HAS_SEC
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select SYS_FSL_SEC_COMPAT_5
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select SYS_FSL_SEC_BE
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config FSL_LSCH3
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select ARCH_MISC_INIT
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select SYS_FSL_CCSR_GUR_LE
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select SYS_FSL_CCSR_SCFG_LE
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select SYS_FSL_ESDHC_LE
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select SYS_FSL_IFC_LE
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select SYS_FSL_PEX_LUT_LE
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bool
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config NXP_LSCH3_2
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bool
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config SYS_FSL_CCSR_GUR_BE
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bool
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config SYS_FSL_CCSR_SCFG_BE
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bool
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config SYS_FSL_PEX_LUT_BE
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bool
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config SYS_FSL_CCSR_GUR_LE
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bool
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config SYS_FSL_CCSR_SCFG_LE
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bool
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config SYS_FSL_ESDHC_LE
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bool
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config SYS_FSL_IFC_LE
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bool
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config SYS_FSL_PEX_LUT_LE
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bool
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menu "Layerscape architecture"
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depends on FSL_LSCH2 || FSL_LSCH3
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config FSL_LAYERSCAPE
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bool
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select ARM_SMCCC
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config HAS_FEATURE_GIC64K_ALIGN
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bool
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default y if ARCH_LS1043A
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config HAS_FEATURE_ENHANCED_MSI
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bool
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default y if ARCH_LS1043A
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config SYS_FSL_ERRATUM_A008997
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bool "Workaround for USB PHY erratum A008997"
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config SYS_FSL_ERRATUM_A009007
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bool
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help
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Workaround for USB PHY erratum A009007
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config SYS_FSL_ERRATUM_A009008
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bool "Workaround for USB PHY erratum A009008"
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config SYS_FSL_ERRATUM_A009798
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bool "Workaround for USB PHY erratum A009798"
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config SYS_FSL_ERRATUM_A050204
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bool "Workaround for USB PHY erratum A050204"
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help
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USB3.0 Receiver needs to enable fixed equalization
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for each of PHY instances in an SOC. This is similar
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to erratum A-009007, but this one is for LX2160A and LX2162A,
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and the register value is different.
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config SYS_FSL_ERRATUM_A010315
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bool "Workaround for PCIe erratum A010315"
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config SYS_FSL_ERRATUM_A010539
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bool "Workaround for PIN MUX erratum A010539"
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config MAX_CPUS
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int "Maximum number of CPUs permitted for Layerscape"
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default 2 if ARCH_LS1028A
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default 4 if ARCH_LS1043A
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default 4 if ARCH_LS1046A
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default 16 if ARCH_LS2080A
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default 8 if ARCH_LS1088A
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default 16 if ARCH_LX2160A
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default 16 if ARCH_LX2162A
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default 1
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help
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Set this number to the maximum number of possible CPUs in the SoC.
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SoCs may have multiple clusters with each cluster may have multiple
|
|
ports. If some ports are reserved but higher ports are used for
|
|
cores, count the reserved ports. This will allocate enough memory
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|
in spin table to properly handle all cores.
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|
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config EMC2305
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|
bool "Fan controller"
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|
help
|
|
Enable the EMC2305 fan controller for configuration of fan
|
|
speed.
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|
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|
config QSPI_AHB_INIT
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|
bool "Init the QSPI AHB bus"
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|
help
|
|
The default setting for QSPI AHB bus just support 3bytes addressing.
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|
But some QSPI flash size up to 64MBytes, so initialize the QSPI AHB
|
|
bus for those flashes to support the full QSPI flash size.
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|
|
|
config FSPI_AHB_EN_4BYTE
|
|
bool "Enable 4-byte Fast Read command for AHB mode"
|
|
help
|
|
The default setting for FlexSPI AHB bus just supports 3-byte addressing.
|
|
But some FlexSPI flash sizes are up to 64MBytes.
|
|
This flag enables fast read command for AHB mode and modifies required
|
|
LUT to support full FlexSPI flash.
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|
|
|
config SYS_CCI400_OFFSET
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|
hex "Offset for CCI400 base"
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|
depends on SYS_FSL_HAS_CCI400
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|
default 0x3090000 if ARCH_LS1088A || ARCH_LS1028A
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|
default 0x180000 if FSL_LSCH2
|
|
help
|
|
Offset for CCI400 base
|
|
CCI400 base addr = CCSRBAR + CCI400_OFFSET
|
|
|
|
config SYS_FSL_HAS_CCI400
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|
bool
|
|
|
|
config SYS_FSL_HAS_CCN504
|
|
bool
|
|
|
|
config SYS_FSL_HAS_CCN508
|
|
bool
|
|
|
|
config SYS_FSL_HAS_DP_DDR
|
|
bool
|
|
help
|
|
Defines the SoC has DP-DDR used for DPAA.
|
|
|
|
config DP_DDR_CTRL
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|
int
|
|
depends on SYS_FSL_HAS_DP_DDR
|
|
default 2 if ARCH_LS2080A
|
|
|
|
config DP_DDR_DIMM_SLOTS_PER_CTLR
|
|
int
|
|
depends on SYS_FSL_HAS_DP_DDR
|
|
default 1 if ARCH_LS2080A
|
|
|
|
config DP_DDR_NUM_CTRLS
|
|
int
|
|
depends on SYS_FSL_HAS_DP_DDR
|
|
default 1 if ARCH_LS2080A
|
|
|
|
config SYS_DP_DDR_BASE
|
|
hex
|
|
depends on SYS_FSL_HAS_DP_DDR
|
|
default 0x6000000000 if ARCH_LS2080A
|
|
|
|
config SYS_DP_DDR_BASE_PHY
|
|
int
|
|
depends on SYS_FSL_HAS_DP_DDR
|
|
default 0 if ARCH_LS2080A
|
|
help
|
|
DDR controller uses this value as the base address for binding.
|
|
It is mapped to CONFIG_SYS_DP_DDR_BASE for core to access.
|
|
|
|
config SYS_NXP_SRDS_3
|
|
bool
|
|
|
|
config FSL_TZASC_1
|
|
bool
|
|
|
|
config FSL_TZASC_2
|
|
bool
|
|
|
|
config FSL_TZASC_400
|
|
bool
|
|
|
|
config FSL_TZPC_BP147
|
|
bool
|
|
endmenu
|
|
|
|
menu "Layerscape clock tree configuration"
|
|
depends on FSL_LSCH2 || FSL_LSCH3
|
|
|
|
config CLUSTER_CLK_FREQ
|
|
int "Reference clock of core cluster"
|
|
depends on ARCH_LS1012A
|
|
default 100000000
|
|
help
|
|
This number is the reference clock frequency of core PLL.
|
|
For most platforms, the core PLL and Platform PLL have the same
|
|
reference clock, but for some platforms, LS1012A for instance,
|
|
they are provided sepatately.
|
|
|
|
config SYS_FSL_PCLK_DIV
|
|
int "Platform clock divider"
|
|
default 1 if ARCH_LS1028A
|
|
default 1 if ARCH_LS1043A
|
|
default 1 if ARCH_LS1046A
|
|
default 1 if ARCH_LS1088A
|
|
default 2
|
|
help
|
|
This is the divider that is used to derive Platform clock from
|
|
Platform PLL, in another word:
|
|
Platform_clk = Platform_PLL_freq / this_divider
|
|
|
|
config SYS_FSL_DSPI_CLK_DIV
|
|
int "DSPI clock divider"
|
|
default 1 if ARCH_LS1043A
|
|
default 2
|
|
help
|
|
This is the divider that is used to derive DSPI clock from Platform
|
|
clock, in another word DSPI_clk = Platform_clk / this_divider.
|
|
|
|
config SYS_FSL_DUART_CLK_DIV
|
|
int "DUART clock divider"
|
|
default 1 if ARCH_LS1043A
|
|
default 4 if ARCH_LX2160A
|
|
default 4 if ARCH_LX2162A
|
|
default 2
|
|
help
|
|
This is the divider that is used to derive DUART clock from Platform
|
|
clock, in another word DUART_clk = Platform_clk / this_divider.
|
|
|
|
config SYS_FSL_I2C_CLK_DIV
|
|
int "I2C clock divider"
|
|
default 1 if ARCH_LS1043A
|
|
default 4 if ARCH_LS1012A
|
|
default 4 if ARCH_LS1028A
|
|
default 8 if ARCH_LX2160A
|
|
default 8 if ARCH_LX2162A
|
|
default 8 if ARCH_LS1088A
|
|
default 2
|
|
help
|
|
This is the divider that is used to derive I2C clock from Platform
|
|
clock, in another word I2C_clk = Platform_clk / this_divider.
|
|
|
|
config SYS_FSL_IFC_CLK_DIV
|
|
int "IFC clock divider"
|
|
default 1 if ARCH_LS1043A
|
|
default 4 if ARCH_LS1012A
|
|
default 4 if ARCH_LS1028A
|
|
default 8 if ARCH_LX2160A
|
|
default 8 if ARCH_LX2162A
|
|
default 8 if ARCH_LS1088A
|
|
default 2
|
|
help
|
|
This is the divider that is used to derive IFC clock from Platform
|
|
clock, in another word IFC_clk = Platform_clk / this_divider.
|
|
|
|
config SYS_FSL_LPUART_CLK_DIV
|
|
int "LPUART clock divider"
|
|
default 1 if ARCH_LS1043A
|
|
default 2
|
|
help
|
|
This is the divider that is used to derive LPUART clock from Platform
|
|
clock, in another word LPUART_clk = Platform_clk / this_divider.
|
|
|
|
config SYS_FSL_SDHC_CLK_DIV
|
|
int "SDHC clock divider"
|
|
default 1 if ARCH_LS1043A
|
|
default 1 if ARCH_LS1012A
|
|
default 2
|
|
help
|
|
This is the divider that is used to derive SDHC clock from Platform
|
|
clock, in another word SDHC_clk = Platform_clk / this_divider.
|
|
|
|
config SYS_FSL_QMAN_CLK_DIV
|
|
int "QMAN clock divider"
|
|
default 1 if ARCH_LS1043A
|
|
default 2
|
|
help
|
|
This is the divider that is used to derive QMAN clock from Platform
|
|
clock, in another word QMAN_clk = Platform_clk / this_divider.
|
|
endmenu
|
|
|
|
config RESV_RAM
|
|
bool
|
|
help
|
|
Reserve memory from the top, tracked by gd->arch.resv_ram. This
|
|
reserved RAM can be used by special driver that resides in memory
|
|
after U-Boot exits. It's up to implementation to allocate and allow
|
|
access to this reserved memory. For example, the reserved RAM can
|
|
be at the high end of physical memory. The reserve RAM may be
|
|
excluded from memory bank(s) passed to OS, or marked as reserved.
|
|
|
|
config SYS_FSL_EC1
|
|
bool
|
|
help
|
|
Ethernet controller 1, this is connected to
|
|
MAC17 for LX2160A and LX2162A or to MAC3 for other SoCs
|
|
Provides DPAA2 capabilities
|
|
|
|
config SYS_FSL_EC2
|
|
bool
|
|
help
|
|
Ethernet controller 2, this is connected to
|
|
MAC18 for LX2160A and LX2162A or to MAC4 for other SoCs
|
|
Provides DPAA2 capabilities
|
|
|
|
config SYS_FSL_ERRATUM_A008336
|
|
bool
|
|
|
|
config SYS_FSL_ERRATUM_A008514
|
|
bool
|
|
|
|
config SYS_FSL_ERRATUM_A008585
|
|
bool
|
|
|
|
config SYS_FSL_ERRATUM_A008850
|
|
bool
|
|
|
|
config SYS_FSL_ERRATUM_A009203
|
|
bool
|
|
|
|
config SYS_FSL_ERRATUM_A009635
|
|
bool
|
|
|
|
config SYS_FSL_ERRATUM_A009660
|
|
bool
|
|
|
|
config SYS_FSL_ERRATUM_A050382
|
|
bool
|
|
|
|
config SYS_FSL_HAS_RGMII
|
|
bool
|
|
depends on SYS_FSL_EC1 || SYS_FSL_EC2
|
|
|
|
config HAS_FSL_XHCI_USB
|
|
bool
|
|
help
|
|
For some SoC (such as LS1043A and LS1046A), USB and QE-HDLC multiplex use
|
|
pins, select it when the pins are assigned to USB.
|
|
|
|
config SYS_FSL_BOOTROM_BASE
|
|
hex
|
|
depends on FSL_LSCH2
|
|
default 0x0
|
|
|
|
config SYS_FSL_BOOTROM_SIZE
|
|
hex
|
|
depends on FSL_LSCH2
|
|
default 0x1000000
|