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	Freescale DDR driver has been used for mpc83xx, mpc85xx, mpc86xx SoCs. The similar DDR controllers will be used for ARM-based SoCs. Signed-off-by: York Sun <yorksun@freescale.com>
		
			
				
	
	
		
			47 lines
		
	
	
		
			983 B
		
	
	
	
		
			C
		
	
	
	
	
	
			
		
		
	
	
			47 lines
		
	
	
		
			983 B
		
	
	
	
		
			C
		
	
	
	
	
	
| /*
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|  * Copyright 2008 Freescale Semiconductor, Inc.
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|  *
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|  * This program is free software; you can redistribute it and/or
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|  * modify it under the terms of the GNU General Public License
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|  * Version 2 as published by the Free Software Foundation.
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|  */
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| 
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| #include <common.h>
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| 
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| #include <fsl_ddr_sdram.h>
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| #include <fsl_ddr_dimm_params.h>
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| 
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| void fsl_ddr_board_options(memctl_options_t *popts,
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| 				dimm_params_t *pdimm,
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| 				unsigned int ctrl_num)
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| {
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| 	/*
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| 	 * Factors to consider for CPO:
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| 	 *	- frequency
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| 	 *	- ddr1 vs. ddr2
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| 	 */
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| 	popts->cpo_override = 0;
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| 
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| 	/*
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| 	 * Factors to consider for write data delay:
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| 	 *	- number of DIMMs
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| 	 *
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| 	 * 1 = 1/4 clock delay
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| 	 * 2 = 1/2 clock delay
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| 	 * 3 = 3/4 clock delay
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| 	 * 4 = 1   clock delay
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| 	 * 5 = 5/4 clock delay
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| 	 * 6 = 3/2 clock delay
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| 	 */
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| 	popts->write_data_delay = 3;
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| 
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| 	/* 2T timing enable */
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| 	popts->twot_en = 1;
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| 
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| 	/*
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| 	 * Factors to consider for half-strength driver enable:
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| 	 *	- number of DIMMs installed
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| 	 */
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| 	popts->half_strength_driver_enable = 0;
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| }
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