u-boot-megous

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Files

Marek Vasut 7544ad0303 ARM: socfpga: Disable D cache in SPL

The bootrom seems to leave the D-cache in messed up state, make sure
the SPL disables it so it can not interfere with operation.

Signed-off-by: Marek Vasut <marex@denx.de>
Cc: Chin Liang See <chin.liang.see@intel.com>
Cc: Dinh Nguyen <dinguyen@kernel.org>
Cc: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
Cc: Tien Fong Chee <tien.fong.chee@intel.com>

2019-03-09 17:59:13 +01:00

arc

ARC: cache: define CONFIG_SYS_CACHELINE_SIZE as ARCH_DMA_MINALIGN

2019-01-25 08:41:09 +03:00

arm

ARM: socfpga: Disable D cache in SPL

2019-03-09 17:59:13 +01:00

m68k

m68k: ColdFire mcf5441x, add eSDHC support

2018-09-16 00:01:13 +02:00

microblaze

arch: types.h: factor out fixed width typedefs to int-ll64.h