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72ab603b20
This patch add clock driver for MediaTek MT7622 SoC. Signed-off-by: Ryder Lee <ryder.lee@mediatek.com> Signed-off-by: Sam Shih <sam.shih@mediatek.com>
272 lines
7.2 KiB
C
272 lines
7.2 KiB
C
/* SPDX-License-Identifier: GPL-2.0-only */
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/*
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* Copyright (c) 2019 MediaTek Inc.
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*/
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#ifndef _DT_BINDINGS_CLK_MT7622_H
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#define _DT_BINDINGS_CLK_MT7622_H
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/* TOPCKGEN */
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/* FIXED_CLKS */
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#define CLK_TOP_TO_U2_PHY 0
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#define CLK_TOP_TO_U2_PHY_1P 1
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#define CLK_TOP_PCIE0_PIPE_EN 2
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#define CLK_TOP_PCIE1_PIPE_EN 3
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#define CLK_TOP_SSUSB_TX250M 4
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#define CLK_TOP_SSUSB_EQ_RX250M 5
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#define CLK_TOP_SSUSB_CDR_REF 6
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#define CLK_TOP_SSUSB_CDR_FB 7
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#define CLK_TOP_SATA_ASIC 8
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#define CLK_TOP_SATA_RBC 9
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/* FIXED_DIVS */
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#define CLK_TOP_TO_USB3_SYS 10
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#define CLK_TOP_P1_1MHZ 11
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#define CLK_TOP_4MHZ 12
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#define CLK_TOP_P0_1MHZ 13
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#define CLK_TOP_TXCLK_SRC_PRE 14
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#define CLK_TOP_RTC 15
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#define CLK_TOP_MEMPLL 16
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#define CLK_TOP_DMPLL 17
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#define CLK_TOP_SYSPLL_D2 18
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#define CLK_TOP_SYSPLL1_D2 19
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#define CLK_TOP_SYSPLL1_D4 20
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#define CLK_TOP_SYSPLL1_D8 21
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#define CLK_TOP_SYSPLL2_D4 22
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#define CLK_TOP_SYSPLL2_D8 23
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#define CLK_TOP_SYSPLL_D5 24
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#define CLK_TOP_SYSPLL3_D2 25
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#define CLK_TOP_SYSPLL3_D4 26
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#define CLK_TOP_SYSPLL4_D2 27
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#define CLK_TOP_SYSPLL4_D4 28
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#define CLK_TOP_SYSPLL4_D16 29
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#define CLK_TOP_UNIVPLL 30
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#define CLK_TOP_UNIVPLL_D2 31
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#define CLK_TOP_UNIVPLL1_D2 32
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#define CLK_TOP_UNIVPLL1_D4 33
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#define CLK_TOP_UNIVPLL1_D8 34
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#define CLK_TOP_UNIVPLL1_D16 35
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#define CLK_TOP_UNIVPLL2_D2 36
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#define CLK_TOP_UNIVPLL2_D4 37
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#define CLK_TOP_UNIVPLL2_D8 38
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#define CLK_TOP_UNIVPLL2_D16 39
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#define CLK_TOP_UNIVPLL_D5 40
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#define CLK_TOP_UNIVPLL3_D2 41
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#define CLK_TOP_UNIVPLL3_D4 42
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#define CLK_TOP_UNIVPLL3_D16 43
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#define CLK_TOP_UNIVPLL_D7 44
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#define CLK_TOP_UNIVPLL_D80_D4 45
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#define CLK_TOP_UNIV48M 46
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#define CLK_TOP_SGMIIPLL 47
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#define CLK_TOP_SGMIIPLL_D2 48
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#define CLK_TOP_AUD1PLL 49
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#define CLK_TOP_AUD2PLL 50
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#define CLK_TOP_AUD_I2S2_MCK 51
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#define CLK_TOP_TO_USB3_REF 52
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#define CLK_TOP_PCIE1_MAC_EN 53
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#define CLK_TOP_PCIE0_MAC_EN 54
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#define CLK_TOP_ETH_500M 55
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/* TOP_MUXES */
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#define CLK_TOP_AXI_SEL 56
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#define CLK_TOP_MEM_SEL 57
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#define CLK_TOP_DDRPHYCFG_SEL 58
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#define CLK_TOP_ETH_SEL 59
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#define CLK_TOP_PWM_SEL 60
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#define CLK_TOP_F10M_REF_SEL 61
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#define CLK_TOP_NFI_INFRA_SEL 62
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#define CLK_TOP_FLASH_SEL 63
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#define CLK_TOP_UART_SEL 64
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#define CLK_TOP_SPI0_SEL 65
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#define CLK_TOP_SPI1_SEL 66
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#define CLK_TOP_MSDC50_0_SEL 67
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#define CLK_TOP_MSDC30_0_SEL 68
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#define CLK_TOP_MSDC30_1_SEL 69
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#define CLK_TOP_A1SYS_HP_SEL 70
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#define CLK_TOP_A2SYS_HP_SEL 71
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#define CLK_TOP_INTDIR_SEL 72
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#define CLK_TOP_AUD_INTBUS_SEL 73
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#define CLK_TOP_PMICSPI_SEL 74
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#define CLK_TOP_SCP_SEL 75
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#define CLK_TOP_ATB_SEL 76
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#define CLK_TOP_HIF_SEL 77
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#define CLK_TOP_AUDIO_SEL 78
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#define CLK_TOP_U2_SEL 79
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#define CLK_TOP_AUD1_SEL 80
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#define CLK_TOP_AUD2_SEL 81
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#define CLK_TOP_IRRX_SEL 82
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#define CLK_TOP_IRTX_SEL 83
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#define CLK_TOP_ASM_L_SEL 84
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#define CLK_TOP_ASM_M_SEL 85
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#define CLK_TOP_ASM_H_SEL 86
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#define CLK_TOP_APLL1_SEL 87
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#define CLK_TOP_APLL2_SEL 88
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#define CLK_TOP_I2S0_MCK_SEL 89
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#define CLK_TOP_I2S1_MCK_SEL 90
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#define CLK_TOP_I2S2_MCK_SEL 91
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#define CLK_TOP_I2S3_MCK_SEL 92
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#define CLK_TOP_APLL1_DIV 93
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#define CLK_TOP_APLL2_DIV 94
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#define CLK_TOP_I2S0_MCK_DIV 95
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#define CLK_TOP_I2S1_MCK_DIV 96
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#define CLK_TOP_I2S2_MCK_DIV 97
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#define CLK_TOP_I2S3_MCK_DIV 98
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#define CLK_TOP_A1SYS_HP_DIV 99
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#define CLK_TOP_A2SYS_HP_DIV 100
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#define CLK_TOP_APLL1_DIV_PD 101
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#define CLK_TOP_APLL2_DIV_PD 102
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#define CLK_TOP_I2S0_MCK_DIV_PD 103
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#define CLK_TOP_I2S1_MCK_DIV_PD 104
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#define CLK_TOP_I2S2_MCK_DIV_PD 105
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#define CLK_TOP_I2S3_MCK_DIV_PD 106
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/* INFRACFG */
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#define CLK_INFRA_DBGCLK_PD 0
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#define CLK_INFRA_TRNG 1
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#define CLK_INFRA_AUDIO_PD 2
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#define CLK_INFRA_IRRX_PD 3
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#define CLK_INFRA_APXGPT_PD 4
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#define CLK_INFRA_PMIC_PD 5
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/* PERICFG */
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#define CLK_PERI_THERM_PD 0
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#define CLK_PERI_PWM1_PD 1
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#define CLK_PERI_PWM2_PD 2
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#define CLK_PERI_PWM3_PD 3
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#define CLK_PERI_PWM4_PD 4
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#define CLK_PERI_PWM5_PD 5
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#define CLK_PERI_PWM6_PD 6
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#define CLK_PERI_PWM7_PD 7
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#define CLK_PERI_PWM_PD 8
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#define CLK_PERI_AP_DMA_PD 9
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#define CLK_PERI_MSDC30_0_PD 10
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#define CLK_PERI_MSDC30_1_PD 11
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#define CLK_PERI_UART0_PD 12
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#define CLK_PERI_UART1_PD 13
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#define CLK_PERI_UART2_PD 14
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#define CLK_PERI_UART3_PD 15
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#define CLK_PERI_BTIF_PD 16
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#define CLK_PERI_I2C0_PD 17
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#define CLK_PERI_I2C1_PD 18
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#define CLK_PERI_I2C2_PD 19
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#define CLK_PERI_SPI1_PD 20
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#define CLK_PERI_AUXADC_PD 21
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#define CLK_PERI_SPI0_PD 22
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#define CLK_PERI_SNFI_PD 23
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#define CLK_PERI_NFI_PD 24
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#define CLK_PERI_NFIECC_PD 25
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#define CLK_PERI_FLASH_PD 26
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#define CLK_PERI_IRTX_PD 27
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/* APMIXEDSYS */
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#define CLK_APMIXED_ARMPLL 0
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#define CLK_APMIXED_MAINPLL 1
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#define CLK_APMIXED_UNIV2PLL 2
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#define CLK_APMIXED_ETH1PLL 3
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#define CLK_APMIXED_ETH2PLL 4
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#define CLK_APMIXED_AUD1PLL 5
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#define CLK_APMIXED_AUD2PLL 6
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#define CLK_APMIXED_TRGPLL 7
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#define CLK_APMIXED_SGMIPLL 8
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/* AUDIOSYS */
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#define CLK_AUDIO_AFE 0
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#define CLK_AUDIO_HDMI 1
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#define CLK_AUDIO_SPDF 2
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#define CLK_AUDIO_APLL 3
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#define CLK_AUDIO_I2SIN1 4
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#define CLK_AUDIO_I2SIN2 5
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#define CLK_AUDIO_I2SIN3 6
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#define CLK_AUDIO_I2SIN4 7
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#define CLK_AUDIO_I2SO1 8
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#define CLK_AUDIO_I2SO2 9
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#define CLK_AUDIO_I2SO3 10
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#define CLK_AUDIO_I2SO4 11
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#define CLK_AUDIO_ASRCI1 12
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#define CLK_AUDIO_ASRCI2 13
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#define CLK_AUDIO_ASRCO1 14
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#define CLK_AUDIO_ASRCO2 15
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#define CLK_AUDIO_INTDIR 16
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#define CLK_AUDIO_A1SYS 17
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#define CLK_AUDIO_A2SYS 18
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#define CLK_AUDIO_UL1 19
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#define CLK_AUDIO_UL2 20
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#define CLK_AUDIO_UL3 21
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#define CLK_AUDIO_UL4 22
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#define CLK_AUDIO_UL5 23
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#define CLK_AUDIO_UL6 24
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#define CLK_AUDIO_DL1 25
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#define CLK_AUDIO_DL2 26
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#define CLK_AUDIO_DL3 27
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#define CLK_AUDIO_DL4 28
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#define CLK_AUDIO_DL5 29
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#define CLK_AUDIO_DL6 30
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#define CLK_AUDIO_DLMCH 31
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#define CLK_AUDIO_ARB1 32
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#define CLK_AUDIO_AWB 33
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#define CLK_AUDIO_AWB3 34
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#define CLK_AUDIO_DAI 35
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#define CLK_AUDIO_MOD 36
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#define CLK_AUDIO_ASRCI3 37
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#define CLK_AUDIO_ASRCI4 38
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#define CLK_AUDIO_ASRCO3 39
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#define CLK_AUDIO_ASRCO4 40
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#define CLK_AUDIO_MEM_ASRC1 41
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#define CLK_AUDIO_MEM_ASRC2 42
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#define CLK_AUDIO_MEM_ASRC3 43
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#define CLK_AUDIO_MEM_ASRC4 44
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#define CLK_AUDIO_MEM_ASRC5 45
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#define CLK_AUDIO_AFE_CONN 46
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#define CLK_AUDIO_NR_CLK 47
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/* SSUSBSYS */
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#define CLK_SSUSB_U2_PHY_1P_EN 0
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#define CLK_SSUSB_U2_PHY_EN 1
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#define CLK_SSUSB_REF_EN 2
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#define CLK_SSUSB_SYS_EN 3
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#define CLK_SSUSB_MCU_EN 4
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#define CLK_SSUSB_DMA_EN 5
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#define CLK_SSUSB_NR_CLK 6
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/* PCIESYS */
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#define CLK_PCIE_P1_AUX_EN 0
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#define CLK_PCIE_P1_OBFF_EN 1
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#define CLK_PCIE_P1_AHB_EN 2
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#define CLK_PCIE_P1_AXI_EN 3
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#define CLK_PCIE_P1_MAC_EN 4
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#define CLK_PCIE_P1_PIPE_EN 5
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#define CLK_PCIE_P0_AUX_EN 6
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#define CLK_PCIE_P0_OBFF_EN 7
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#define CLK_PCIE_P0_AHB_EN 8
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#define CLK_PCIE_P0_AXI_EN 9
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#define CLK_PCIE_P0_MAC_EN 10
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#define CLK_PCIE_P0_PIPE_EN 11
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#define CLK_SATA_AHB_EN 12
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#define CLK_SATA_AXI_EN 13
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#define CLK_SATA_ASIC_EN 14
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#define CLK_SATA_RBC_EN 15
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#define CLK_SATA_PM_EN 16
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#define CLK_PCIE_NR_CLK 17
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/* ETHSYS */
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#define CLK_ETH_HSDMA_EN 0
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#define CLK_ETH_ESW_EN 1
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#define CLK_ETH_GP2_EN 2
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#define CLK_ETH_GP1_EN 3
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#define CLK_ETH_GP0_EN 4
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/* SGMIISYS */
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#define CLK_SGMII_TX250M_EN 0
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#define CLK_SGMII_RX250M_EN 1
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#define CLK_SGMII_CDR_REF 2
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#define CLK_SGMII_CDR_FB 3
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#endif /* _DT_BINDINGS_CLK_MT7622_H */
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